52 S29GLxxxN MirrorBitTM Flash Family 27631A4 May 13, 2004

Advance Information

that the ACC function and unlock bypass modes are not available when the SecSi

Sector is enabled.

The SecSi sector address space in this device is allocated as follows:

The system accesses the SecSi Sector through a command sequence (see “Write

Protect (WP#)”). After the system has written the Enter SecSi Sector command

sequence, it may read the SecSi Sector by using the addresses normally occupied

by the first sector (SA0). This mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until power is removed from the de-

vice. On power-up, or following a hardware reset, the device reverts to sending

commands to sector SA0.

Customer Lockable: SecSi Sector NOT Programmed or Protected

At the Factory

Unless otherwise specified, the device is shipped such that the customer may

program and protect the 256-byte SecSi sector.

The system may program the SecSi Sector using the write-buffer, accelerated

and/or unlock bypass methods, in addition to the standard programming com-

mand sequence. See Command Definitions.

Programming and protecting the SecSi Sector must be used with caution since,

once protected, there is no procedure available for unprotecting the SecSi Sector

area and none of the bits in the SecSi Sector memory space can be modified in

any way.

The SecSi Sector area can be protected using one of the following procedures:

 Write the three-cycle Enter SecSi Sector Region command sequence, and

then follow the in-system sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V

or V

. This allows in-system protec-

tion of the SecSi Sector without raising any device pin to a high voltage. Note

that this method is only applicable to the SecSi Sector.

 To verify the protect/unprotect status of the SecSi Sector, follow the algo-

rithm shown in Figure 1.

Once the SecSi Sector is programmed, locked and verified, the system must write

the Exit SecSi Sector Region command sequence to return to reading and writing

within the remainder of the array.

Factory Locked: SecSi Sector Programmed and Protected At the

Factory

In devices with an ESN, the SecSi Sector is protected when the device is shipped

from the factory. The SecSi Sector cannot be modified in any way. An ESN Factory

Locked device has an 16-byte random ESN at addresses 000000h–000007h.

Please contact your sales representative for details on ordering ESN Factory

Locked devices.

Customers may opt to have their code programmed by the factory through the

ExpressFlash service (Express Flash Factory Locked). The devices are then

shipped from the factory with the SecSi Sector permanently locked. Contact your

sales representative for details on using the ExpressFlash service.

SecSi Sector Address Range Customer Lockable ESN Factory Locked

ExpressFlash

Factory Locked

000000h–000007h

Determined by customer

ESN

ESN or determined by

customer

000008h–00007Fh Unavailable Determined by customer

May 13, 2004 27631A4 S29GLxxxN MirrorBitTM Flash Family 53

Advance Information

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting the first or

last sector group without using V

. Write Protect is one of two functions provided

by the WP#/ACC input.

If the system asserts V

on the WP#/ACC pin, the device disables program and

erase functions in the first or last sector group independently of whether those

sector groups were protected or unprotected using the method described in“Ad-

vanced Sector Protection” section on page 46. Note that if WP#/ACC is at V

when the device is in the standby mode, the maximum input load current is in-

creased. See the table in “DC Characteristics” section on page 86.

If the system asserts V

on the WP#/ACC pin, the device reverts to

whether the first or last sector was previously set to be protected or un-

protected using the method described in “Sector Group Protection and

Unprotection”. Note that WP# has an internal pullup; when uncon-

nected, WP# is at V

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes (refer to Tables 16 and 17 for

command definitions). In addition, the following hardware data protection mea-

sures prevent accidental erasure or programming, which might otherwise be

caused by spurious system level signals during V

power-up and power-down

transitions, or from system noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not accept any write cycles. This pro-

tects data during V

power-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to the read

mode. Subsequent writes are ignored until V

is greater than V

LKO

. The system

must provide the proper signals to the control pins to prevent unintentional writes

when V

is greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write

cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V

, CE# = V

or WE# =

. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = V

during power up, the device does not accept

commands on the rising edge of WE#. The internal state machine is automatically

reset to the read mode on power-up.

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

54 S29GLxxxN MirrorBitTM Flash Family 27631A4 May 13, 2004

Advance Information

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h, any time the device is ready to read array data.

The system can read CFI information at the addresses given in Tables 8-11. To

terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 8–11. The system must write the reset

command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication

100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alter-

natively, contact your sales representative for copies of these documents.

Part #	S29GL256N10TFI020
Description	NOR Flash Parallel 3.3V 256M-bit 32M x 8/16M x 16 100ns 56
Category	IC
Availability	In Stock
Qty	2

S29GL256N10TFI020

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