CS4373A

DS699F2 13

DIGITAL CHARACTERISTICS (CONT.)

Notes: 25. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the device automatically enters

a power-down state.

26. MSYNC is generated by the CS5376A digital filter and is latched on MCLK rising edge, synchronization

instant (t

) on next MCLK rising edge.

27. TDATA can be delayed from 0 to 63 full bit periods by the CS5376A test bit stream generator. The timing

diagram shows no TBSDATA delay.

Parameter Symbol Min Typ Max Unit

Master Clock

MCLK Frequency (Note 25)f

CLK

-2.048- MHz

MCLK Period (Note 25)t

mclk

-488- ns

MCLK Duty Cycle (Note 8)MCLK

40 - 60 %

MCLK Rise Time (Note 8)t

RISE

- - 50 ns

MCLK Fall Time (Note 8)t

FALL

- - 50 ns

MCLK Jitter (In-band or aliased in-band) (Note 8)MCLK

IBJ

--300ps

MCLK Jitter (Out-of-band) (Note 8)MCLK

OBJ

--1 ns

Master Sync

MSYNC Setup Time to MCLK rising (Note 8, 26)t

mss

20 122 - ns

MSYNC Period (Note 8, 26)t

msync

40 976 - ns

MSYNC Hold Time after MCLK falling (Note 8, 26)t

msh

20 122 - ns

MSYNC Instant to TDATA Start (Note 8, 27)t

tdata

- 1220 - ns

CS4373A

14 DS699F2

DIGITAL CHARACTERISTICS (CONT.)

MCLK

MSYNC

TDATA

(2.048 MHz)

(256 kHz)

SYNC

Figure 2. System Timing Diagram

MCLK

MSYNC

TDATA

(2.048 MHz)

(256 kHz)

mss

mclk

msync

msh

tdata

Figure 3. MCLK / MSYNC Timing Detail

CS4373A

DS699F2 15

POWER SUPPLY CHARACTERISTICS

Notes: 28. All outputs unloaded. Digital inputs forced to VD or DGND respectively.

29. Power supply rejection is characterized by applying a 100 mVp-p 50-Hz sine wave to each supply.

Parameter Symbol Min Typ Max Unit

AC Mode Supply Current (MODE = 1, 2, 3, 6)

Analog Power Supply Current (Note 28)I

-810mA