
X24C00
7
Bus Timing
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
LOW
t
SU:STO
t
R
t
BUF
SCL
SDA IN
SDA OUT
t
DH
t
AA
t
F
t
HIGH
3836 FHD F10
WRITE CYCLE LIMITS
Symbol Parameter Min. Max. Units
t
WR
(4)
Write Cycle Time 5 ms
3836 PGM T09
Write Cycle Timing
3836 ILL F11.1
SDA
t
WR
SCL
D0
START
CONDTION
X24C00
ADDRESS
Note: (4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the
write cycle, the X24C00 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start
conditions.