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24C00/P

Part # 24C00/P
Description EEPROM SERL-I2C 128BIT 16X8 5V 8PDIP - Rail/Tube
Category IC
Availability Out of Stock
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1 + $0.12000



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

X24C00
1
128 Bit X24C00 16 x 8 Bit
Serial E
2
PROM
© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3836-1.5 6/10/96 T2/C1/D0 NS
DESCRIPTION
The X24C00 is a CMOS 128 bit serial E
2
PROM, inter-
nally organized as 16 x 8. The X24C00 features a serial
interface and software protocol allowing operation on a
simple two wire bus.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
The X24C00 is fabricated with Xicor’s Advanced CMOS
Floating Gate technology.
FEATURES
2.7V to 5.5V Power Supply
128 Bit Serial E
2
PROM
Low Power CMOS
—Active Current Less Than 3mA
—Standby Current Less Than 50µA
Internally Organized 16 x 8
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
Byte Mode Write
Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
Push/Pull Output
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
Available Packages
—8-Lead MSOP
—8-Lead PDIP
—8-Lead SOIC
FUNCTIONAL DIAGRAM
CONTROL
LOGIC
INPUT/
OUTPUT
BUFFER
SCL
SDA
COMMAND/ADDRESS
REGISTER
SHIFT REGISTER
MEMORY ARRAY
3836 FHD F01
PIN CONFIGURATION
APPLICATION NOTES
AVAILABLE
AN4 • AN12 • AN22 • AN26 • AN32
V
CC
NC
SCL
SDA
3836 FHD F02.1
NC
NC
NC
V
SS
1
2
3
4
8
7
6
5
X24C00
MSOP/DIP/SOIC
2
X24C00
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is a push/pull output and does not
require the use of a pull-up resistor.
PIN NAMES
Symbol Description
NC No Connect
V
SS
Ground
V
CC
Supply Voltage
SDA Serial Data
SCL Serial Clock
3836 PGM T01
DEVICE OPERATION
The X24C00 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. There-
fore, the X24C00 will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C00 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
A start may be issued to terminate the input of a control
word or the input of data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start
cannot be generated while the part is outputting data.
Starts are also inhibited while a write is in progress.
Stop Condition
The stop condition is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is used to reset
the device during a command or data input sequence
and will leave the device in the standby mode. As with
starts, stops are inhibited when outputting data and
while a write is in progress.
Write Operation
The byte write operation is initiated with a start condition.
The start condition is followed by an eight bit control byte
which consists of a two bit write command (0,1), four
address bits, and two “don’t care” bits (Figure 3).
X24C00
3
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
3836 FHD F03
Figure 2. Definition of Start and Stop Conditions
SCL
SDA
START CONDITION STOP CONDITION
3836 FHD F04
Figure 3. Control Byte
START
C1
C2 A3 A2 A1 A0 XX XX
3836 FHD F05
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