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PLDC20G10B
PLDC20G10
Document #: 38-03010 Rev. *A Page 2 of 14
Functional Description
Cypress PLDC20G10 uses an advanced 0.8-micron CMOS
technology and a proven EPROM cell as the programmable
element. This technology and the inherent advantage of being
able to program and erase each cell enhances the reliability
and testability of the circuit. This reduces the burden on the
customer to test and to handle rejects.
A preload function allows the registered outputs to be preset
to any pattern during testing. Preload is important for testing
the functionality of the Cypress PLD device.
20G10 Functional Description
The PLDC20G10 is a generic 24-pin device that can be
programmed to logic functions that include but are not limited
to: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4,
20L2, and 20V8. Thus, the PLDC20G10 provides significant
design, inventory and programming flexibility over dedicated
24-pin devices. It is executed in a 24-pin 300-mil molded DIP
and a 300-mil windowed cerDIP. It provides up to 22 inputs and
10 outputs. When the windowed cerDIP is exposed to UV light,
the 20G10 is erased and then can be reprogrammed.
The programmable output cell provides the capability of
defining the architecture of each output individually. Each of
the 10 output cells may be configured with registered or combi-
natorial outputs, active HIGH or active LOW outputs, and
product term or Pin 13 generated output enables. Three archi-
tecture bits determine the configurations as shown in the
Configuration Table and in Figures 1 through 8. A total of eight
different configurations are possible, with the two most
common shown in Figure 3 and Figure 5. The default or unpro-
grammed state is registered/active/LOW/Pin 11 OE. The
entire programmable output cell is shown in the next section.
The architecture bit ‘C1’ controls the registered/combinatorial
option. In either combinatorial or registered configuration, the
output can serve as an I/O pin, or if the output is disabled, as
an input only. Any unused inputs should be tied to ground. In
either registered or combinatorial configuration, the output of
the register is fed back to the array. This allows the creation of
control-state machines by providing the next state. The
register is clocked by the signal from Pin 1. The register is
initialized on power up to Q
output LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen
with architecture bit ‘C2’. The OE signal may be generated
within the array, or from the external OE
(Pin 13). The Pin 13
allows direct control of the outputs, hence having faster
enable/disable times.
Each output cell can be configured for output polarity. The
output can be either active HIGH or active LOW. This option is
controlled by architecture bit ‘C0’.
Along with this increase in functional density, the Cypress
PLDC20G10 provides lower-power operation through the use
of CMOS technology and increased testability with a register
preload feature.
Selection Guide
I
CC
(mA) t
PD
(ns) t
S
(ns) t
CO
(ns)
Generic
Part Number Com/Ind Mil Com/Ind Mil Com/Ind Mil Com/Ind Mil
20G10B–15 70 15 12 10
20G10B–20 70 100 20 20 12 15 12 15
20G10B–25 100 25 18 15
20G10–25 55 25 15 15
20G10–30 80 30 20 20
20G10–35 55 35 30 25
20G10–40 80 40 35 25
