Figure 3. Test Circuit and Denitions for the Driver Common-Mode Output Voltage
D
OUT+
D
OUT–
D
IN
Driver (continued)
2 V
1.4 V
0.8 V
100%
80%
20%
0%
0 V
V
OD(H)
V
OD(L)
Output
V
OD
100 Ω
±1%
C
L
= 10 pF
(2 Places)
t
PHL
t
PLH
t
f
t
r
D
OUT+
D
OUT–
D
IN
D
IN
NOTE A: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
£ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns . C
L
includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T.
V
OC
C
L
= 10 pF
(2 Places)
3 V
0 V
V
OC(PP)
V
OC(SS)
V
OC
49.9 Ω, ±1% (2 Places)
NOTE A: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
£ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns . C
L
includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T. The measurement of V
OC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 4. Receiver Voltage Denitions
