■
Independent 32 Lword (128 byte) read and
64 Lword (256 byte) write FIFOs
■
Deferred reads, deferred writes, posted
writes, read ahead, and programmable read
prefetch counter
■
Programmable READY# time out
and recovery
Advanced Performance Features Common to
DMA, Direct Master, and Direct Slave
■
Zero wait state PCI and local bus bursts
■
Deep FIFOs prolong bursts
■
Unaligned PCI and local bus transfers of
any byte length
■
On-the-fly Endian conversion
■
Programmable local bus wait states
■
Parity checking on both buses
Messaging
■
Provides industry standard I
2
O r1.5
messaging unit
■
Supports general-purpose messaging for
proprietary message schemes
– Eight 32-bit mailbox registers for polled
environments
– Two 32-bit doorbell registers for interrupt
driven environments
Embedded Host Features
■
PCI arbiter supports 7 external masters
■
Reset and interrupt signals configurable for
embedded host operation
■
Type 0/1 Configuration support allows
local bus master to configure PCI bus
and devices
Package
■
256-ball fine pitch PBGA (FPBGA)
– 17 mm x 17 mm, 1.00 mm ball pitch
– Low power 2.5V CMOS core
– 3.3V I/O, 5V tolerant
– Industrial temperature range operation
– IEEE 1149.1 JTAG boundary scan
Backward Compatibility
■
The PCI 9056 register set is backward
compatible with the PCI 9054, with
new registers added for functionality
enhancements
Related PLX Products
■
Support for 64-bit, 66MHz PCI with 32-bit,
66MHz C, J, and M Local Bus Support is
provided by the PCI 9656
– See the PCI 9656 product brief for details
Serial EEPROM
■
Stores configuration register power on,
reset values
■
An alternative to expansion ROM for
storing Vital Product Data (VPD)
■
Supports 2 Kbit/4 Kbit microwire devices
with sequential read
Data Pipe Architecture
DMA
Service DMA descriptors, mastering on both
bus interfaces during data transfer
■
Two independent channels provide flexible
prioritization scheme
■
Each channel has its own bi-directional
64 Lword (256 byte) deep FIFO
■
Block Mode services a single DMA
descriptor in PCI 9056 registers
■
Scatter/Gather Mode services DMA
descriptor linked lists in memory
– Burst descriptors from PCI or local
bus memory
– Descriptor lists either linear (static)
or circular (dynamic) with Valid bit
semaphore control
■
Direct Hardware DMA controls
– Demand Mode to pause/resume
– End of Transfer (EOT) to abort
■
Programmable local bus burst length,
including infinite
– Enhanced M Mode supports bursts beyond
PowerQUICC 16 byte limit
Direct Master
Service local bus masters by mastering on
the PCI bus
■
Two local bus address spaces map to
PCI bus: one to memory; one to I/O
■
Generate all PCI memory and I/O transac-
tion types, including Memory Write and
Invalidate (MWI)
■
Independent 32 Lword (128 byte) read
and 64 Lword (256 byte) write FIFOs
■
Read ahead and programmable read
prefetch counter
■
PowerQUICC deferred reads and IDMA
(M mode only)
Direct Slave
Service PCI bus masters by mastering on
the local bus
■
Two general-purpose and one expansion
ROM PCI address spaces map to local
bus memory
– Each address space may specify 8-, 16-, or
32-bit local bus data transfers
PCI 9056 Features
The PCI 9056 32-bit, 66MHz PCI I/O accelera-
tor is the most advanced, 32-bit general-pur-
pose bus mastering device available for
Motorola MPC 850/860 PowerQUICC and
generic 32-bit, 66MHz local bus based
designs. The PCI 9056 incorporates PLX’s
industry leading Data Pipe Architecture
technology, featuring DMA engines, program-
mable Direct Master and Direct Slave data
transfer modes, and PCI messaging functions.
Interfaces
PCI
■
32-bit, 66MHz r2.2 operation
– Zero wait state bursts to 264 MB/s
– Dual Address Cycle (DAC) support as a
PCI bus master
– Vital Product Data (VPD)
– 3.3V I/O, 5V tolerant
■
PICMG 2.1 r2.0 Hot Swap Silicon
– Programming Interface 0 (PI=0)
– Bias Voltage Support
– Early Power Support
– Intially Not Responding Support
■
PCI Hot Plug r1.0
■
PCI Power Management r1.1
– Supports D0, D1, D2, D3
HOT
, and D3
COLD
power states
– D3
COLD
Power Management Event (PME)
generation to meet PC 2001 Windows
98/2000 communication adapter logo
certification requirements
Local Bus
■
Three local bus options on the device
– M Mode: Motorola MPC 850/860
PowerQUICC and PowerPC 80x/82x
– C Mode: De-multiplexed address and data
buses for Intel i960(r), DSPs, custom ASICs
and FPGAs, and others
– J Mode: Multiplexed address and data buses
for Intel i960, IBM PowerPC 401, IDT
RC32364, DSPs, PLX IOP 480, and others
■
32-bit, 66MHz operation
– Zero wait state bursts to 264 MB/s
– 3.3V I/O, 5V tolerant
– Asynchronous clock inputs to PCI and
local bus
