7−3
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER TERMINALS OPERATION TEST CONDITIONS MIN MAX UNIT
3.3 V
I
OH
= −0.5 mA 0.9 V
CC
5 V
I
OH
= −2 mA 2.4
V
V
High-level output voltage
3.3 V
I
OH
= −0.15 mA 0.9 V
CC
High-level output voltage
PC Card
5 V
I
OH
= −0.15 mA 2.4
V
Miscellaneous
I
= −4 mA V
−0.
3.3 V
I
OL
= 1.5 mA 0.1 V
CC
5 V
I
OL
= 6 mA 0.55
V
Low-level output voltage
3.3 V
I
OL
= 0.7 mA 0.1 V
CC
V
5 V
I
OL
= 0.7 mA 0.55
Miscellaneous
I
OL
= 4 mA 0.5
High-impedance, low-level output
3.6 V V
I
= V
CC
−1
I
OZL
High-impedance, low-level output
current
Output terminals
5.25 V V
I
= V
CC
−1
µA
High-impedance, high-level output
3.6 V
V
I
= V
CC
†
10
I
OZH
High-impedance, high-level output
current
Output terminals
5.25 V
V
I
= V
CC
†
25
µA
Input terminals V
I
= GND −1
I
Low-level input current
I/O terminals
V
I
= GND −10
µA
Pullup terminals V
I
= GND −330
3.6 V
V
I
= V
CC
‡
10
Input terminals
5.25 V
V
I
= V
CC
‡
20
I
IH
High-level input current
3.6 V V
I
= V
CC
‡
10
µA
I/O terminals
5.25 V V
I
= V
CC
‡
25
Pulldown 5.25 V V
I
= V
CC
‡
30
†
For PCI and miscellaneous terminals, V
I
= V
CCP
. For PC Card terminals, V
I
= V
CCCB
.
‡
For I/O terminals, input leakage (I
IL
and I
IH
) includes I
OZ
leakage of the disabled output.
7.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS MIN MAX UNIT
t
c
Cycle time, PCLK t
cyc
30 ns
t
w(H)
Pulse duration (width), PCLK high t
high
11 ns
t
w(L)
Pulse duration (width), PCLK low t
low
11 ns
t
r
, t
f
Slew rate, PCLK ∆v/∆t 1 4 V/ns
t
w
Pulse duration (width), PRST t
rst
1 ms
t
su
Setup time, PCLK active at end of PRST t
rst-clk
100 ms
