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PCI1510GGU

Part # PCI1510GGU
Description PCI TO PC CARD CONTROLLER - Trays
Category IC
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Technical Document


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5−7
Bit
7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: ExCA power control—82365SL-DF support
Offset: CardBus socket address + 802h; ExCA offset 02h
Type: Read-only, Read/Write
Default: 00h
Table 5−5. ExCA Power Control Register Description—82365SL-DF Support
BIT SIGNAL TYPE FUNCTION
7 COE RW
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the controller. This bit is encoded as:
0 = 16-bit PC Card outputs disabled (default)
1 = 16-bit PC Card outputs enabled
6−5 RSVD R Reserved. Bits 6 and 5 return 00b when read.
4−3 EXCAVCC RW
V
CC
. Bits 4 and 3 request changes to card V
CC
. This field is encoded as:
00 = 0 V (default)
01 = 0 V reserved
10 = 5 V
11 = 3.3 V
2 RSVD R Reserved. Bit 2 returns 0b when read.
1−0 EXCAVPP RW
V
PP
. Bits 1 and 0 request changes to card V
PP
. The controller ignores this field unless V
CC
to the socket is
enabled. This field is encoded as:
00 = No connection (default)
01 = V
CC
10 = 12 V
11 = Reserved
5−8
5.4 ExCA Interrupt and General Control Register
The ExCA interrupt and general control register controls interrupt routing for I/O interrupts, as well as other critical
16-bit PC Card functions. See Table 5−6 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: ExCA interrupt and general control
Offset: CardBus socket address + 803h; ExCA offset 03h
Type: Read/Write
Default: 00h
Table 5−6. ExCA Interrupt and General Control Register Description
BIT SIGNAL TYPE FUNCTION
7 RINGEN RW
Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as:
0 = Ring indicate disabled (default)
1 = Ring indicate enabled
6 RESET RW
Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6
affects 16-bit cards only. This bit is encoded as:
0 = RESET signal asserted (default)
1 = RESET signal deasserted
5 CARDTYPE RW
Card type. Bit 5 indicates the PC card type. This bit is encoded as:
0 = Memory PC Card installed (default)
1 = I/O PC Card installed
4 CSCROUTE RW
PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed
to PCI interrupts. When low, the card status change interrupts are routed using bits 7−4 (CSCSELECT field)
in the ExCA card status-change interrupt configuration register (ExCA offset 05h/45h/805h, see
Section 5.6). This bit is encoded as:
0 = CSC interrupts are routed by ExCA registers (default)
1 = CSC interrupts are routed to PCI interrupts
3−0 INTSELECT RW
Card interrupt select for I/O PC Card functional interrupts. Bits 3−0 select the interrupt routing for I/O
PC Card functional interrupts. This field is encoded as:
0000 = No interrupt routing (default). CSC interrupts are routed to PCI interrupts. This bit setting is
ORed with bit 4 (CSCROUTE) for backward compatibility.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0100 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
5−9
5.5 ExCA Card Status-Change Register
The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC
Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt
source is disabled, the corresponding bit in this register always reads 0b. When an interrupt source is enabled, the
corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to
the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt
service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of
two methods: a read of this register or an explicit write back of 1b to the status bit. The choice of these two methods
is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (ExCA offset 1E/5E/81E, see
Section 5.20). See Table 5−7 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: ExCA card status-change
Offset: CardBus socket address + 804h; ExCA offset 04h
Type: Read-only
Default: 00h
Table 5−7. ExCA Card Status-Change Register Description
BIT SIGNAL TYPE FUNCTION
7−4 RSVD R Reserved. Bits 7−4 return 0h when read.
3 CDCHANGE R
Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface.
This bit is encoded as:
0 = No change detected on either CD1 or CD2
1 = Change detected on either CD1 or CD2
2 READYCHANGE R
Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of an
interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now
ready to accept new data. This bit is encoded as:
0 = No low-to-high transition detected on READY (default)
1 = Detected low-to-high transition on READY
When a 16-bit I/O card is installed, bit 2 is always 0b.
1 BATWARN R
Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the
source of an interrupt was due to a battery-low warning condition. This bit is encoded as:
0 = No battery warning condition (default)
1 = Detected battery warning condition
When a 16-bit I/O card is installed, bit 1 is always 0b.
0 BATDEAD R
Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates
whether the source of an interrupt was due to a battery dead condition. This bit is encoded as:
0 = STSCHG deasserted (default)
1 = STSCHG
asserted
Ring indicate. When the controller is configured for ring indicate operation, bit 0 indicates the status of
RI
.
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