5−1

5 ExCA Compatibility Registers

The ExCA registers implemented in the PCI1510 controller are register-compatible with the Intel 82365SL−DF

PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data

scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the

register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O

base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy-mode base address

Figure 5−1 for an ExCA I/O mapping illustration.

CardBus Socket/ExCA Base Address

16-Bit Legacy-Mode Base Address

10h

44h

00h

3Fh

Offset

Index

Host I/O Space

Data

PC Card A

ExCA

Registers

PCI1510 Configuration Registers

Offset

Figure 5−1. ExCA Register Access Through I/O

The controller also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI memory

space. They are located through the CardBus socket/ExCA base-address register (PCI offset 10h, see Section 4.12)

at memory offset 800h. See Figure 5−2 for an ExCA memory mapping illustration. This illustration also identifies the

CardBus socket register mapping, which is mapped into the same 4-K window at memory offset 00h.

CardBus Socket/ExCA Base Address

16-Bit Legacy-Mode Base Address

10h

44h

PCI1510 Configuration Registers

CardBus

Socket

Registers

Host

Memory Space

00h

ExCA

Registers

20h

800h

844h

OffsetOffset

Figure 5−2. ExCA Register Access Through Memory

The interrupt registers in the ExCA register set, as defined by the 82365SL−DL specification, control such card

functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing

registers and the host interrupt signaling method selected for the controller to ensure that all possible interrupts can

potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt

5−2

signaling are the ExCA interrupt and general control register (ExCA offset 03h/43h/803h, see Section 5.4) and the

ExCA card status-change interrupt configuration register (05h/45h/805h, see Section 5.6).

Access to I/O mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions

of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and

offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity.

Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These

are regions of host memory space into which the card memory space is mapped. These windows are defined by start,

end, and offset addresses programmed in the ExCA registers described in this section. Table 5−1 identifies each

ExCA register and its respective ExCA offset. Memory windows have 4-Kbyte granularity.

Table 5−1. ExCA Registers and Offsets

EXCA REGISTER NAME

PCI MEMORY ADDRESS

OFFSET (HEX)

ExCA OFFSET

(HEX)

Identification and revision 800 00

Interface status 801 01

Power control 802 02

Interrupt and general control 803 03

Card status change 804 04

Card status-change interrupt configuration 805 05

Address window enable 806 06

I / O window control 807 07

I / O window 0 start-address low byte 808 08

I / O window 0 start-address high byte 809 09

I / O window 0 end-address low byte 80A 0A

I / O window 0 end-address high byte 80B 0B

I / O window 1 start-address low byte 80C 0C

I / O window 1 start-address high byte 80D 0D

I / O window 1 end-address low byte 80E 0E

I / O window 1 end-address high byte 80F 0F

Memory window 0 start-address low byte 810 10

Memory window 0 start-address high byte 811 11

Memory window 0 end-address low byte 812 12

Memory window 0 end-address high byte 813 13

Memory window 0 offset-address low byte 814 14

Memory window 0 offset-address high byte 815 15

Card detect and general control 816 16

Reserved 817 17

Memory window 1 start-address low byte 818 18

Memory window 1 start-address high byte 819 19

Memory window 1 end-address low byte 81A 1A

Memory window 1 end-address high byte 81B 1B

Memory window 1 offset-address low byte 81C 1C

Memory window 1 offset-address high byte 81D 1D

Global control 81E 1E

Reserved 81F 1F

Memory window 2 start-address low byte 820 20

Memory window 2 start-address high byte 821 21

Memory window 2 end-address low byte 822 22

5−3

Table 5−1. ExCA Registers and Offsets (Continued)

EXCA REGISTER NAME

PCI MEMORY ADDRESS

OFFSET (HEX)

ExCA OFFSET

(HEX)

Memory window 2 end-address high byte 823 23

Memory window 2 offset-address low byte 824 24

Memory window 2 offset-address high byte 825 25

Reserved 826 26

Reserved 827 27

Memory window 3 start-address low byte 828 28

Memory window 3 start-address high byte 829 29

Memory window 3 end-address low byte 82A 2A

Memory window 3 end-address high byte 82B 2B

Memory window 3 offset-address low byte 82C 2C

Memory window 3 offset-address high byte 82D 2D

Reserved 82E 2E

Reserved 82F 2F

Memory window 4 start-address low byte 830 30

Memory window 4 start-address high byte 831 31

Memory window 4 end-address low byte 832 32

Memory window 4 end-address high byte 833 33

Memory window 4 offset-address low byte 834 34

Memory window 4 offset-address high byte 835 35

I/O window 0 offset-address low byte 836 36

I/O window 0 offset-address high byte 837 37

I/O window 1 offset-address low byte 838 38

I/O window 1 offset-address high byte 839 39

Reserved 83A 3A

Reserved 83B 3B

Reserved 83C 3C

Reserved 83D 3D

Reserved 83E 3E

Reserved 83F 3F

Memory window page 0 840 −

Memory window page 1 841 −

Memory window page 2 842 −

Memory window page 3 843 −

Memory window page 4 844 −

A bit description table, typically included when a register contains bits of more than one type or purpose, indicates

bit field names, which appear in the signal column; a detailed field description, which appears in the function column;

and field access tags, which appear in the type column of the bit description table. Table 4−2 describes the field

access tags.

Part #	PCI1510GGU
Description	PCI TO PC CARD CONTROLLER - Trays
Category	IC
Availability	Out of Stock
Qty	0

PCI1510GGU

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