4−25

4.42 General-Purpose Event Enable Register

The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven

until the corresponding status bit is cleared and the event is serviced. The GPE

can only be signaled if one of the

multifunction terminals, MFUNC6−MFUNC0, is configured for GPE

signaling. See Table 4−17 for a complete

description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Offset: AAh

Type: Read-only, Read/Write

Default: 0000h

Table 4−17. General-Purpose Event Enable Register Description

BIT SIGNAL TYPE FUNCTION

15 ZV0_EN RW

PC Card ZV enable. When bit 15 is set, a GPE is signaled on a change in status of bit 6 (ZVENABLE) in

the card control register (PCI offset 91h, see Section 4.32).

14−12 RSVD R Reserved. Bits 14−12 return 000b when read.

11 PWR_EN RW

Power change enable. When bit 11 is set, a GPE is signaled on when software has changed the power

state.

10−9 RSVD R Reserved. Bits 10 and 9 return 00b when read.

8 VPP12_EN RW

12-V V

request enable. When bit 8 is set, a GPE is signaled when software has changed the requested

level to or from 12 V.

7−5 RSVD R Reserved. Bits 7−5 return 000b when read.

4 GP4_EN RW

GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5

terminal input level if configured as GPI4.

3 GP3_EN RW

GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4

terminal input level if configured as GPI3.

2 GP2_EN RW

GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2

terminal input if configured as GPI2.

1 GP1_EN RW

GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1

terminal input if configured as GPI1.

0 GP0_EN RW

GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0

terminal input if configured as GPI0.

4−26

4.43 General-Purpose Input Register

The general-purpose input register provides the logical value of the data input from the GPI terminals, MFUNC5,

MFUNC4, and MFUNC2−MFUNC0. See Table 4−18 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Default 0 0 0 0 0 0 0 0 0 0 0 X X X X X

Offset: ACh

Type: Read-only

Default: 00XXh

Table 4−18. General-Purpose Input Register Description

BIT SIGNAL TYPE FUNCTION

15−5 RSVD R Reserved. Bits 15−5 return 0s when read.

4 GPI4_DATA R GPI4 data bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal.

3 GPI3_DATA R GPI3 data bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal.

2 GPI2_DATA R GPI2 data bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal.

1 GPI1_DATA R GPI1 data bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal.

0 GPI0_DATA R GPI0 data bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal.

4.44 General-Purpose Output Register

The general-purpose output register is used for control of the general-purpose outputs. See Table 4−19 for a

complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Offset: AEh

Type: Read-only, Read/Write

Default: 0000h

Table 4−19. General-Purpose Output Register Description

BIT SIGNAL TYPE FUNCTION

15−5 RSVD R Reserved. Bits 15−5 return 0s when read.

4 GPO4_DATA RW

GPO4 data bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5

terminal if configured as GPO4. Read transactions return the last data value written.

3 GPO3_DATA RW

GPIO3 data bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4

terminal if configured as GPO3. Read transactions return the last data value written.

2 GPO2_DATA RW

GPO2 data bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2

terminal if configured as GPO2. Read transactions return the last data value written.

1 GPO1_DATA RW

GPO1 data bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1

terminal if configured as GPO1. Read transactions return the last data value written.

0 GPO0_DATA RW

GPO0 data bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0

terminal if configured as GPO0. Read transactions return the last data value written.

4−27

4.45 Serial-Bus Data Register

The serial-bus data register is for programmable serial-bus byte reads and writes. This register represents the data

when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data,

the serial bus index register must be programmed with the byte address, the serial-bus slave address must be

programmed with the 7-bit slave address, and the read/write indicator bit must be reset.

On byte reads, the byte address is programmed into the serial-bus index register, the serial bus slave address register

must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the

serial bus control and status register (PCI offset B3h, see Section 4.48) must be polled until clear. Then the contents

of this register are valid read data from the serial bus interface. See Table 4−20 for a complete description of the

Bit 7 6 5 4 3 2 1 0

Default 0 0 0 0 0 0 0 0

Offset: B0h

Type: Read/Write

Default: 00h

Table 4−20. Serial-Bus Data Register Description

BIT SIGNAL TYPE FUNCTION

7−0 SBDATA RW

Serial-bus data. This bit field represents the data byte in a read or write transaction on the serial interface.

On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid.

4.46 Serial-Bus Index Register

The serial-bus index register is for programmable serial-bus byte reads and writes. This register represents the byte

address when generating cycles on the serial-bus interface. To write a byte, the serial-bus data register must be

programmed with the data, this register must be programmed with the byte address, and the serial-bus slave address

On byte reads, the word address is programmed into this register, the serial-bus slave address must be programmed

with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial-bus control and

status register (see Section 4.48) must be polled until clear. Then the contents of the serial-bus data register are valid

read data from the serial-bus interface. See Table 4−21 for a complete description of the register contents.

Bit 7 6 5 4 3 2 1 0

Default 0 0 0 0 0 0 0 0

Offset: B1h

Type: Read/Write

Default: 00h

Table 4−21. Serial-Bus Index Register Description

BIT SIGNAL TYPE FUNCTION

7−0 SBINDEX RW Serial-bus index. This bit field represents the byte address in a read or write transaction on the serial interface.

Part #	PCI1510GGU
Description	PCI TO PC CARD CONTROLLER - Trays
Category	IC
Availability	Out of Stock
Qty	0

PCI1510GGU

Related Items

Technical Document