4−23
4.39 Power-Management Control/Status Register Bridge Support Extensions
The power-management control/status register bridge support extensions support PCI bridge specific functionality.
See Table 4−15 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Default 1 1 0 0 0 0 0 0
Register: Power-management control/status register bridge support extensions
Offset: A6h
Type: Read-only
Default: C0h
Table 4−15. Power-Management Control/Status Register Bridge Support Extensions Description
BIT SIGNAL TYPE FUNCTION
7 BPCC_EN R
BPCC_Enable. Bus power/clock control enable. This bit returns 1b when read.
This bit is encoded as:
0 = Bus power/clock control is disabled
1 = Bus power/clock control is enabled (default)
A 0b indicates that the bus power/clock control policies defined in the PCI Bus Power Management
Interface Specification are disabled. When the bus power/clock control enable mechanism is disabled,
the bridge power-management control/status register power state field (see Section 4.38, bits 1−0)
cannot be used by the system software to control the power or the clock of the bridge secondary bus. A
1b indicates that the bus power/clock control mechanism is enabled.
6 B2_B3 R
B2/B3 support for D3
hot
. The state of this bit determines the action that is to occur as a direct result of
programming the function to D3
hot
. This bit is only meaningful if bit 7 (BPCC_EN) is a 1b. This bit is
encoded as:
0 = When the bridge is programmed to D3
hot
, its secondary bus has its power removed (B3)
1 = When the bridge function is programmed to D3
hot
, its secondary bus PCI clock is
stopped (B2) (default)
5−0 RSVD R Reserved. Bits 5−0 return 000000b when read.
4.40 Power-Management Data Register
The power-management data register returns 00h when read, because the CardBus function does not report dynamic
data.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: Power-management data
Offset: A7h
Type: Read-only
Default: 00h
