4−16

4.30 Multifunction Routing Register

The multifunction routing register is used to configure the MFUNC0−MFUNC6 terminals. These terminals may be

configured for various functions. All multifunction terminals default to the general-purpose input configuration. This

loaded through a serial bus EEPROM. See Table 4−8 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Offset: 8Ch

Type: Read-only, Read/Write

Default: 0000 1000h

Table 4−8. Multifunction Routing Register Description

BIT SIGNAL TYPE FUNCTION

31−28 RSVD R Bits 31−28 return 0h when read.

27−24 MFUNC6 RW

Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal

as follows:

0000 = RSVD

†

0100 = IRQ4 1000 = IRQ8 1100 = IRQ12

0001 = CLKRUN

0101 = IRQ5 1001 = IRQ9 1101 = IRQ13

0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14

0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15

23−20 MFUNC5 RW

Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal

as follows:

0000 = GPI4

†

0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT

0001 = GPO4 0101 = D3_STAT

1001 = D3_STAT 1101 = LED_SKT

0010 = PCGNT

0110 = ZVSTAT 1010 = IRQ10 1110 = GPE

0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15

19−16 MFUNC4 RW

Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal

as follows:

NOTE: When the serial bus mode is implemented by pulling up the VCCD0

and VCCD1 terminals, the

MFUNC4 terminal provides the SCL signaling.

0000 = GPI3

†

0100 = IRQ4 1000 = CAUDPWM 1100 = RI_OUT

0001 = GPO3 0101 = IRQ5 1001 = IRQ9 1101 = LED_SKT

0010 = LOCK

PCI 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE

0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = D3_STAT

15−12 MFUNC3 RW

Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal

as follows:

0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12

0001 = IRQSER

†

0101 = IRQ5 1001 = IRQ9 1101 = IRQ13

0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14

0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15

11−8 MFUNC2 RW

Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal

as follows:

0000 = GPI2

†

0100 = IRQ4 1000 = CAUDPWM 1100 = RI_OUT

0001 = GPO2 0101 = IRQ5 1001 = IRQ9 1101 = D3_STAT

0010 = PCREQ 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE

0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ7

4−17

Table 4−8. Multifunction Routing Register Description (Continued)

BIT SIGNAL TYPE FUNCTION

7−4 MFUNC1 RW

Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal

as follows:

NOTE: When the serial bus mode is implemented by pulling up the VCCD0

and VCCD1 terminals, the

MFUNC1 terminal provides the SDA signaling.

0000 = GPI1

†

0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT

0001 = GPO1 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13

0010 = D3_STAT

0110 = ZVSTAT 1010 = IRQ10 1110 = GPE

0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15

3−0 MFUNC0 RW

Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal

as follows:

0000 = GPI0

†

0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT

0001 = GPO0 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13

0010 = INTA

0110 = ZVSTAT 1010 = IRQ10 1110 = GPE

0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15

†

Default value

4.31 Retry Status Register

The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set

when the controller retries a PCI or CardBus master request and the master does not return within 2

PCI clock

cycles. The flags are cleared by writing a 1b to the bit. These bits are expected to be incorporated into the PCI

command, PCI status, and bridge control registers by the PCI SIG. See Table 4−9 for a complete description of the

Bit 7 6 5 4 3 2 1 0

Default 1 1 0 0 0 0 0 0

Offset: 90h

Type: Read-only, Read/Write, Read/Clear

Default: C0h

Table 4−9. Retry Status Register Description

BIT SIGNAL TYPE FUNCTION

7 PCIRETRY RW

PCI retry timeout counter enable. Bit 7 is encoded:

0 = PCI retry counter disabled

1 = PCI retry counter enabled (default)

6 CBRETRY RW

CardBus retry timeout counter enable. Bit 6 is encoded:

0 = CardBus retry counter disabled

1 = CardBus retry counter enabled (default)

5 TEXP_CBB RC

CardBus target B retry expired. Write a 1b to clear bit 5.

0 = Inactive (default)

1 = Retry has expired

4 RSVD R Reserved. Bit 4 returns 0b when read.

3 TEXP_CBA RC

CardBus target A retry expired. Write a 1b to clear bit 3.

0 = Inactive (default)

1 = Retry has expired

2 RSVD R Reserved. Bit 2 returns 0b when read.

1 TEXP_PCI RC

PCI target retry expired. Write a 1b to clear bit 1.

0 = Inactive (default)

1 = Retry has expired

0 RSVD R Reserved. Bit 0 returns 0b when read.

4−18

4.32 Card Control Register

The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register. See

Table 4−10 for a complete description of the register contents.

Bit 7 6 5 4 3 2 1 0

Default 0 0 0 0 0 0 0 0

Offset: 91h

Type: Read-only, Read/Write, Read/Clear

Default: 00h

Table 4−10. Card Control Register Description

BIT SIGNAL TYPE FUNCTION

7 RIENB RW

Ring indicate output enable.

0 = Disables any routing of RI_OUT

signal (default)

1 = Enables RI_OUT

signal for routing to the RI_OUT/PME terminal, when RIMUX is set to 0b,

and for routing to MFUNC2 or MFUNC4

6 ZVENABLE RW

Compatibility ZV mode enable. When set, the corresponding PC Card socket interface ZV terminals enter

a high-impedance state. This bit defaults to 0b.

5 RSVD RW Reserved. Do not change default value.

4−3 RSVD R Reserved. Bits 4 and 3 return 00b when read.

2 AUD2MUX RW

CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding

multifunction terminal which may be configured for CAUDPWM.

1 SPKROUTEN RW

Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The

SPKROUT terminal drives data only when the SPKROUTEN bit is set. This bit is encoded as:

0 = SPKR to SPKROUT not enabled

1 = SPKR

to SPKROUT enabled

0 IFG RC

Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a

functional interrupt is signaled from a PC Card interface. Write back a 1b to clear this bit.

0 = No PC Card functional interrupt detected (default).

1 = PC Card functional interrupt detected.

Part #	PCI1510GGU
Description	PCI TO PC CARD CONTROLLER - Trays
Category	IC
Availability	Out of Stock
Qty	0

PCI1510GGU

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