4−15
Table 4−7. System Control Register Description (Continued)
BIT SIGNAL TYPE FUNCTION
15 MRBURSTDN RW
Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to
burst downstream.
0 = Downstream memory read burst is disabled
1 = Downstream memory read burst is enabled (default)
14 MRBURSTUP RW
Memory read burst enable upstream. When bit 14 is set, the controller allows memory read transactions
to burst upstream.
0 = Upstream memory read burst is disabled (default)
1 = Upstream memory read burst is enabled
13 SOCACTIVE R
Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and
is cleared upon read of this status bit.
0 = No socket activity (default)
1 = Socket activity
12 RSVD R Reserved. Bit 12 returns 1b when read.
11 PWRSTREAM R
Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch
is in progress and a powering change has been requested. This bit is cleared when the power stream is
complete.
0 = Power stream is complete and delay has expired
1 = Power stream is in progress
10 DELAYUP R
Power-up delay in progress status. When set, bit 10 indicates that a power-up stream has been sent to
the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay
has expired.
9 DELAYDOWN R
Power-down delay in progress status. When set, bit 9 indicates that a power-down stream has been sent
to the power switch and proper power may not yet be stable. This bit is cleared when the power-down
delay has expired.
8 INTERROGATE R
Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when
interrogation completes.
0 = Interrogation not in progress (default)
1 = Interrogation in progress
7 AUTOPWRSWEN R/W
Auto power-switch enable
0 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is disabled (default)
1 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is enabled
6 PWRSAVINGS RW
Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock,
then the applicable CB state machine will not be clocked.
5 SUBSYSRW RW
Subsystem ID (PCI offset 42h, see Section 4.27), subsystem vendor ID (PCI offset 40H, see
Section 4.26), ExCA identification and revision (ExCA offset 00h/40h/800h, see Section 5.1) registers
read/write enable.
0 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read/write
1 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read-only
(default)
4 CB_DPAR RW
CardBus data parity SERR signaling enable
0 = CardBus data parity not signaled on PCI SERR
1 = CardBus data parity signaled on PCI SERR
3 RSVD RW Reserved. Do not change the default value.
2 EXCAPOWER RW
ExCA power-control bit.
0 = Enables 3.3 V
1 = Enables 5 V
1 KEEPCLK RW
Keep clock. This bit works with PCI and CB CLKRUN protocols.
0 = Allows normal functioning of both CLKRUN
protocols (default)
1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN
protocols
0 RIMUX RW
RI_OUT/PME multiplex enable.
0 = RI_OUT
and PME are both routed to the RI_OUT/PME terminal. If both functions are are enabled
at the same time, the terminal becomes RI_OUT
only and PME assertions are not seen.
1 = Only PME
is routed to the RI_OUT/PME terminal.
