4−3
4.4 Command Register
The command register provides control over the controller interface to the PCI bus. All bit functions adhere to the
definitions in PCI Local Bus Specification. See Table 4−3 for a complete description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Command
Offset: 04h
Type: Read-only, Read/Write
Default: 0000h
Table 4−3. Command Register Description
BIT SIGNAL TYPE FUNCTION
15−10 RSVD R Reserved. Bits 15−10 return 00 0000b when read.
9 FBB_EN R
Fast back-to-back enable. The controller does not generate fast back-to-back transactions; therefore, bit 9
returns 0b when read.
8 SERR_EN RW
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can
be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the
controller to report address parity errors.
0 = Disable SERR
output driver (default)
1 = Enable SERR
output driver
7 STEP_EN R
Address/data stepping control. The controller does not support address/data stepping; therefore, bit 7 is
hardwired to 0b.
6 PERR_EN RW
Parity error response enable. Bit 6 controls the controller response to parity errors through PERR. Data
parity errors are indicated by asserting PERR
, whereas address parity errors are indicated by asserting
SERR
.
0 = The controller ignores detected parity error (default)
1 = The controller responds to detected parity errors
5 VGA_EN RW
VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette
registers.
4 MWI_EN R
Memory write-and-invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory
write-and-Invalidate commands. The controller does not support memory write-and-invalidate commands,
but uses memory write commands instead; therefore, this bit is hardwired to 0b.
3 SPECIAL R
Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The controller does
not respond to special cycle operations; therefore, this bit is hardwired to 0b.
2 MAST_EN RW
Bus master control. Bit 2 controls whether or not the controller can act as a PCI bus initiator (master). The
controller can take control of the PCI bus only when this bit is set.
0 = Disables the controller from generating PCI bus accesses (default)
1 = Enables the controller to generate PCI bus accesses
1 MEM_EN RW
Memory space enable. Bit 1 controls whether or not the controller can claim cycles in PCI memory space.
0 = Disables the controller from responding to memory space accesses (default)
1 = Enables the controller to respond to memory space accesses
0 IO_EN RW
I/O space control. Bit 0 controls whether or not the controller can claim cycles in PCI I/O space.
0 = Disables the controller from responding to I/O space accesses (default)
1 = Enables the controller to respond to I/O space accesses
