3−20

• D3

hot

− Low-power state. Transition state before D3

cold

• D3

cold

− PME signal-generation capable. Main power is removed and VAUX is available.

• D3

off

− No power and completely non-functional

NOTE:

In the D0-uninitialized state, the controller does not generate PME

and/or interrupts. When the IO_EN and

MEM_EN bits (bits 0 and 1) of the command register (PCI offset 04h, see Section 4.4) are both set, the

controller switches the state to D0-active. Transition from D3

cold

to the D0-uninitialized state happens at

the deassertion of PRST

. The assertion of GRST forces the controller to the D0-uninitialized state

immediately.

The PWR_STATE bits (bits 0−1) of the power-management control/status register (PCI offset A4h, see

Section 4.38) only code for four power states, D0, D1, D2, and D3

hot

. The differences between the three

D3 states is invisible to the software because the controller is not accessible in the D3

cold

or D3

off

state.

Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power

state of the originating bridge device.

For the operating system (OS) to manage the device power states on the PCI bus, the PCI function should support

four power-management operations. These operations are:

• Capabilities reporting

• Power status reporting

• Setting the power state

• System wake up

The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of

capabilities in addition to the standard PCI capabilities is indicated by a 1b in bit 4 (CAPLIST) of the status register

(PCI offset 06h, see Section 4.5).

The capabilities pointer provides access to the first item in the linked list of capabilities. For the controller, a CardBus

bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first

byte of each capability register block is required to be a unique ID of that capability. PCI power management has been

assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more

items in the list, then the next item pointer must be set to 0b. The registers following the next item pointer are specific

to the capability of the function. The PCI power-management capability implements the register block outlined in

Table 3−11.

Table 3−11. Power-Management Registers

Power-management capabilities Next-item pointer Capability ID A0h

Power-management data

Power-management

control/status bridge

support extensions

Power-management control/status A4h

The power management capabilities register (PCI offset A2h, see Section 4.37) provides information on the

capabilities of the function related to power management. The power-management control/status register (PCI offset

A4h, see Section 4.38) enables control of power-management states and enables/monitors power-management

events. The data register is an optional register that can provide dynamic data.

For more information on PCI power management, see the PCI Bus Power Management Interface Specification for

PCI to CardBus Bridges.

3.8.9 CardBus Bridge Power Management

The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in

December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power

Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed

in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3

hot

or D3

cold

without losing wake-up context (also called PME context).

3−21

The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges

for D3 wake up are as follows:

• Preservation of device context. The specification states that a reset must occur during the transition from

D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear

the PME

context registers.

• Power source in D3

cold

if wake-up support is required from this state.

The PCI1510 controller addresses these D3 wake-up issues in the following manner:

• Two resets are provided to handle preservation of PME

context bits:

− Global reset (GRST

) is used only on the initial boot up of the system after power up. It places the

controller in its default state and requires BIOS to configure the device before becoming fully functional.

− PCI reset (PRST

) has dual functionality based on whether PME is enabled or not. If PME is enabled,

then PME

context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.

Please see the master list of PME

context bits in Section 3.8.11.

• Power source in D3

cold

if wake-up support is required from this state. Since V

is removed in D3

cold

, an

auxiliary power source must be supplied to the V

terminals. Consult the PCI14xx Implementation Guide

for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for

further information.

3.8.10 ACPI Support

The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique

pieces of hardware to be described to the ACPI driver. The controller offers a generic interface that is compliant with

ACPI design rules.

Two doublewords of general-purpose ACPI programming bits reside in PCI configuration space at offset A8h. The

programming model is broken into status and control functions. In compliance with ACPI, the top level event status

and enable bits reside in the general-purpose event status register (PCI offset A8h, see Section 4.41) and

general-purpose event enable register (PCI offset AAh, see Section 4.42). The status and enable bits are

implemented as defined by ACPI and illustrated in Figure 3−17.

Event Output

Event Input

Enable Bit

Status Bit

Figure 3−17. Block Diagram of a Status/Enable Cell

The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the

pending status bit. The control method can then control the hardware by manipulating the hardware control bits or

by investigating child status bits and calling their respective control methods. A hierarchical implementation would

be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report

events.

For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.

3−22

3.8.11 Master List of PME Context Bits and Global Reset-Only Bits

If the PME enable bit (bit 8) of the power-management control/status register (PCI offset A4h, see section 4.38) is

asserted, then the assertion of PRST

will not clear the following PME context bits. If the PME enable bit is not asserted,

then the PME

context bits are cleared with PRST. The PME context bits are:

• Bridge control register (PCI offset 3Eh): bit 6

• System control register (PCI offset 80h): bits 10, 9, 8

• Power-management control/status register (PCI offset A4h): bits 15, 8

• ExCA power control register (ExCA offset 802h): bits 7, 5

†

, 4−3, 1−0 (

†

82365SL mode only)

• ExCA interrupt and general control register (ExCA offset 803h): bits 6−5

• ExCA card status change register (ExCA offset 804h): bits 11−8, 3−0

• ExCA card status-change-interrupt configuration register (ExCA offset 805h): bits 3−0

• CardBus socket event register (CardBus offset 00h): bits 3−0

• CardBus socket mask register (CardBus offset 04h): bits 3−0

• CardBus socket present state register (CardBus offset 08h): bits 13−7, 5−1

• CardBus socket control register (CardBus offset 10h): bits 6−4, 2−0

Global reset places all registers in their default state regardless of the state of the PME

enable bit. The GRST signal

is gated only by the SUSPEND

signal. This means that assertion of SUSPEND blocks the GRST signal internally,

thus preserving all register contents. The registers cleared only by GRST

are:

• Status register (PCI offset 06h): bits 15−11, 8

• Secondary status register (PCI offset 16h): bits 15−11, 8

• Interrupt pin register (PCI offset 3Dh): bits 1,0

• Subsystem vendor ID register (PCI offset 40h): bits 15–0

• Subsystem ID register (PCI offset 42h): bits 15–0

• PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31–1

• System control register (PCI offset 80h): bits 31–29, 27–13, 11, 6−0

• Multifunction routing register (PCI offset 8Ch): bits 27−0

• Retry status register (PCI offset 90h): bits 7−5, 3, 1

• Card control register (PCI offset 91h): bits 7−5, 2−0

• Device control register (PCI offset 92h): bits 7−5, 3−0

• Diagnostic register (PCI offset 93h): bits 7−0

• Power management capabilities register (PCI offset A2h): bit 15

• General-purpose event status register (PCI offset A8h): bits 15−14

• General-purpose event enable register (PCI offset AAh): bits 15−14, 11, 8, 4−0

Part #	PCI1510GGU
Description	PCI TO PC CARD CONTROLLER - Trays
Category	IC
Availability	Out of Stock
Qty	0

PCI1510GGU

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