3−17
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the controller, various features are designed into
the device to allow implementation of popular power-saving techniques. These features and techniques are
discussed in this section.
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR)
The controller requires 2.5-V core voltage. The core power can be supplied by the controller itself using the internal
LDO-VR. The core power can alternatively be supplied by an external power supply through the VR_PORT terminal.
Table 3−10 lists the requirements for both the internal core power supply and the external core power supply.
Table 3−10. Requirements for Internal/External 2.5-V Core Power Supply
SUPPLY V
CC
VR_EN VR_PORT NOTE
Internal 3.3 V GND 2.5-V output Internal 2.5-V LDO-VR is enabled. A 1.0-µF bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
External 3.3 V V
CC
2.5-V input Internal 2.5-V LDO-VR is disabled. An external 2.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1-µF bypass capacitor on the VR_PORT terminal is required.
3.8.2 Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the controller.
CLKRUN
signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this
is not always available to the system designer, and alternate power-saving features are provided. For details on the
CLKRUN
protocol see the PCI Mobile Design Guide.
The controller does not permit the central resource to stop the PCI clock under any of the following conditions:
• Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
• The 16-bit PC Card- resource manager is busy.
• The CardBus master state machine is busy. A cycle may be in progress on CardBus.
• The master is busy. There may be posted data from CardBus to PCI in the controller.
• Interrupts are pending.
• The CardBus CCLK for either socket has not been stopped by the CCLKRUN
manager.
The controller restarts the PCI clock using the CLKRUN
protocol under any of the following conditions:
• A 16-bit PC Card IREQ
or a CardBus CINT has been asserted by either card.
• A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG
/RI event occurs in either socket.
• A CardBus attempts to start the CCLK using CCLKRUN
.
• A CardBus card arbitrates for the CardBus bus using CREQ
.
3.8.3 CardBus PC Card Power Management
The controller implements its own card power-management engine that can turn off the CCLK to a socket when there
is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN
interface
to control this clock management.
3.8.4 16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN
bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) bits are provided for 16-bit
PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The
power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN
bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function
when there is no card activity.
NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
