3−13
This format must be followed for the controller to load initializations from a serial EEPROM. All bit fields must be
considered when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the controller. All hardware address bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit (Figure 3−8) assumes the 1010b high-address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
3.6.4 Accessing Serial-Bus Devices Through Software
The controller provides a programming mechanism to control serial bus devices through software. The programming
is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−6 lists the registers used
to program a serial-bus device through software.
Table 3−6. PCI1510 Registers Used to Program Serial-Bus Devices
PCI OFFSET REGISTER NAME DESCRIPTION
B0h Serial-bus data Contains the data byte to send on write commands or the received data byte on read commands.
B1h Serial-bus index
The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
B2h
Serial-bus slave
address
Write transactions to this register initiate a serial-bus transaction. The slave device address and the
R/W
command selector are programmed through this register.
B3h
Serial-bus control
and status
Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol-select bit is programmed through this register.
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
controller. The controller provides several interrupt signaling schemes to accommodate the needs of a variety of
platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and
industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the
CardBus socket register set provides interrupt control for the CardBus PC Card functions. The controller is, therefore,
backward compatible with existing interrupt control register definitions, and new registers have been defined where
required.
The controller detects PC Card interrupts and events at the PC Card interface and notifies the host controller using
one of several interrupt signaling protocols. To simplify the discussion of interrupts in the controller, PC Card interrupts
are classified either as card status change (CSC) or as functional interrupts.
The method by which any type of interrupt is communicated to the host interrupt controller varies from system to
system. The controller offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type
IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel
PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All
interrupt signaling is provided through the seven multifunction terminals, MFUNC0−MFUNC6.
3.7.1 PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
controller and may warrant notification of host card and socket services software for service. CSC events include both
card insertion and removal from the PC Card socket, as well as transitions of certain PC Card signals.
