3−8

3.5.7 SPKROUT and CAUDPWM Usage

SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for

I/O mode, the BVD2 terminal becomes SPKR

. This terminal is also used in CardBus binary audio applications, and

is referred to as CAUDIO. SPKR

passes a TTL-level digital audio signal to the controller. The CardBus CAUDIO signal

also can pass a single-amplitude binary waveform. The binary audio signal from the PC Card socket is used in the

controller to produce SPKROUT. This output is enabled by bit 1 (SPKROUTEN) in the card control register (PCI offset

91h, see Section 4.32).

Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio chips

may not support both modes on one terminal and may have a separate terminal for binary and PWM. The

implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2

(AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM terminal to

CAUDPWM. See Section 4.30, Multifunction Routing Register, for details on configuring the MFUNC terminals.

Figure 3−6 provides an illustration of a sample application using SPKROUT and CAUDPWM.

Speaker

Subsystem

BINARY_SPKR

System

Core Logic

PCI1510

CAUDPWM

SPKROUT

PWM_SPKR

Figure 3−6. Sample Application of SPKROUT and CAUDPWM

3.5.8 LED Socket Activity Indicators

The socket activity LED is provided to indicate when a PC Card is being accessed. The LED_SKT signal can be routed

to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate

socket activity. See Section 4.30, Multifunction Routing Register,

for details on configuring the multifunction

terminals.

The active-high LED signal is driven for 64-ms. When the LED is not being driven high, it is driven to a low state. Either

of the two circuits shown in Figure 3−7 can be implemented to provide LED signaling, and the board designer must

implement the circuit that best fits the application.

The LED activity signal is valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity

signal is pulsed when READY/IREQ

is low. For CardBus cards, the LED activity signal is pulsed if CFRAME, IRDY,

or CREQ

are active.

3−9

PCI1510

Application-

Specific Delay

Current Limiting

R ≈ 500 Ω

PCI1510

Current Limiting

R ≈ 500 Ω

LED

Figure 3−7. Two Sample LED Circuits

As indicated, the LED signal is driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED

appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND

signal is

asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.

If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains

driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven.

3.5.9 CardBus Socket Registers

The controller contains all registers for compatibility with the PC Card Standard. These registers exist as the CardBus

socket registers and are listed in Table 3−4.

Table 3−4. CardBus Socket Registers

Socket event 00h

Socket mask 04h

Socket present state 08h

Socket force event 0Ch

Socket control 10h

Reserved 14h−1Ch

Socket power management 20h

3.6 Serial-Bus Interface

The controller provides a serial-bus interface to load subsystem identification information and selected register

defaults from a serial EEPROM, and to provide a PC Card power-switch interface alternative. The serial-bus interface

is compatible with various I

C and SMBus components.

3.6.1 Serial-Bus Interface Implementation

To enable the serial interface, a pullup resistor must be implemented on the VCCD0 and VCCD1 terminals and the

appropriate pullup resistors must be implemented on the SDA and SCL signals, that is, the MFUNC1 and MFUNC4

terminals. When the interface is detected, bit 3 (SBDETECT) in the serial bus control and status register (PCI offset

B3h, see Section 4.48) is set. The SBDETECT bit is cleared by a writeback of 1b.

The controller implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). When

pullup resistors are provided on the VCCD0

and VCCD1 terminals, the SCL signal is mapped to the MFUNC4 terminal

and the SDA signal is mapped to the MFUNC1 terminal. The controller drives SCL at nearly 100 kHz during data

3−10

transfers, which is the maximum specified frequency for standard-mode I

C. The serial EEPROM must be located

at address A0h. Figure 3−8 illustrates an example application implementing the two-wire serial bus.

Serial

EEPROM

PCI1510

MFUNC4

MFUNC1

SCL

SDA

VCCD0

VCCD1

5 V

Figure 3−8. Serial EEPROM Application

Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other

devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches

are discussed in the sections that follow.

3.6.2 Serial-Bus Interface Protocol

The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−8.

The controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode I

C using 7-bit

addressing.

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start

condition, which is signaled when the SDA line transitions to low state while SCL is in the high state, as illustrated

in Figure 3−9. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high

transition of SDA while SCL is in the high state, as shown in Figure 3−9. Data on SDA must remain stable during the

high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control

signals, that is, a start or a stop condition.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 3−9. Serial-Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is

unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by

the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−10

illustrates the acknowledge protocol.

Part #	PCI1510GGU
Description	PCI TO PC CARD CONTROLLER - Trays
Category	IC
Availability	Out of Stock
Qty	0

PCI1510GGU

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Technical Document