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PCI1510GGU

Part # PCI1510GGU
Description PCI TO PC CARD CONTROLLER - Trays
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

3−5
PCI1510
(PC Card
Controller)
12 V
Power Supply
V
PP1
V
PP2
V
CC
V
CC
PC Card
TPS2211A
5 V
3.3 V
VCCD0
12V
5V
3.3V
AVPP
AVCC
Supervisor
SHDN
SHDN
VCCD1
VPPD0
VPPD1
Figure 3−3. TPS2211A Typical Application
3.5.3 Zoomed Video Support
The controller allows for the implementation of zoomed video (ZV) for PC Cards. Zoomed video is supported by
setting bit 6 (ZVENABLE) in the card control register (PCI offset 91h, see Section 4.32). Setting this bit puts 16-bit
PC Card address lines A25−A4 of the PC Card interface in the high-impedance state. These lines can then transfer
video and audio data directly to the appropriate controller. Card address lines A3−A0 can still access PC Card CIS
registers for PC Card configuration. Figure 3−4 illustrates a ZV implementation.
CRT
VGA
Controller
Audio
Codec
PCI1510
19 4
Zoomed Video
Port
PCM
Audio
Input
PCI Bus
PC Card
Interface
Video
Audio
19
4
PC Card
Motherboard
Speakers
Figure 3−4. Zoomed Video Implementation Using the PCI1510 Controller
Not shown in Figure 3−4 is the multiplexing scheme used to route a socket ZV source to the graphics controller. The
controller provides ZVSTAT and ZVSEL0
signals on the multifunction terminals to switch external bus drivers.
Figure 3−5 shows an implementation for switching between two ZV streams using external logic.
3−6
ZVSTAT
PCI1510
ZVSEL0
Figure 3−5. Zoomed Video Switching Application
Figure 3−5 illustrates an implementation using standard three-state bus drivers with active-low output enables.
ZVSEL0
is an active-low output indicating that the socket ZV mode is enabled.
3.5.4 Standardized Zoomed-Video Register Model
The standardized zoomed-video register model is defined for the purpose of standardizing the ZV port control for PC
Card controllers across the industry. The following list summarizes the standardized zoomed-video register model
changes to the existing PC Card register set.
Socket present state register (CardBus socket address + 08h, see Section 6.3)
Bit 27 (ZVSUPPORT) has been added. The platform BIOS can set this bit via the socket force event register
(CardBus socket address + 0Ch, see Section 6.4) to define whether zoomed video is supported on the
socket by the platform.
Socket force event register (CardBus socket address + 0Ch, see Section 6.4)
Bit 27 (FZVSUPPORT) has been added. The platform BIOS can use this bit to set the ZVSUPPORT bit in
the socket present state register (CardBus socket address + 08h, see Section 6.3) to define whether
zoomed video is supported on the socket by the platform.
Socket control register (CardBus socket address +10h, see Section 6.5)
Bit 11 (ZV_ACTIVITY) has been added. This bit is set when zoomed video is enabled for the PC Card socket.
Bit 10 (STDZVREG) has been added. This bit defines whether the PC Card controller supports the
standardized zoomed-video register model.
Bit 9 (ZVEN) is provided for software to enable or disable zoomed video.
If the STDZVEN bit (bit 0) in the diagnostic register (PCI offset 93h, see Section 4.34) is 1b, then the standardized
zoomed video register model is disabled. For backward compatibility, even if the STDZVEN bit is 0b (enabled), the
controller allows software to access zoomed video through the legacy address in the card control register (PCI offset
91h, see Section 4.32), or through the new register model in the socket control register (CardBus socket address +
10h, see Section 6.5).
3.5.4.1 Zoomed-Video Card Insertion and Configuration Procedure
1. A zoomed-video PC Card is inserted into an empty slot.
2. The card is detected and interrogated appropriately.
3−7
There are two types of PC Card controllers to consider.
Legacy controller not using the standardized ZV register model
Software reads bit 10 (STDZVREG) of the socket control register (CardBus socket address + 10h) to
determine if the standardized zoomed-video register model is supported. If the bit returns 0b, then software
must use legacy code to enable zoomed video.
Newer controller that uses the standardized ZV register model
Software reads bit 10 (STDZVREG) of the socket control register (CardBus socket address + 10h) to
determine if the standardized zoomed-video register model is supported. If the bit returns 1b, then software
can use the process/register model detailed in Table 3−2 to enable zoomed video.
Table 3−2. Zoomed-Video Card Interrogation
ZVSUPPORT ZV_ACTIVITY ACTION
1 0 Set ZVEN to enable zoomed video.
1 1
Display a user message such as, The zoomed video protocol required by this PC Card application is al-
ready in use by another card.
0 X
Display a user message such as, This platform does not support the zoomed-video protocol required by
this PC Card application.
3.5.5 Internal Ring Oscillator
The internal ring oscillator provides an internal clock source for the controller so that neither the PCI clock nor an
external clock is required in order for the controller to power down a socket or interrogate a PC Card. This internal
oscillator can be enabled by setting bit 27 (P2CCLK) of the system control register (PCI offset 80h, see Section 4.29)
to 1b. This function is enabled by default.
3.5.6 Integrated Pullup Resistors
The PC Card Standard (release 7.2) requires pullup resistors on various terminals to support both CardBus and 16-bit
card configurations. Unlike the PCI12XX, PCI1450, and PCI4450 controllers which required external pullup resistors,
the PCI1510 controller has integrated all of these pullup resistors. The I/O buffer on the BVD1(STSCHG
)//CSTSCHG
terminal has the capability to switch either pullup or pulldown. The pullup resistor is turned on when a 16-bit PC Card
is inserted, and the pulldown resistor is turned on when a CardBus PC Card is inserted. This prevents unexpected
CSTSCHG signal assertion. The integrated pullup resistors are listed in Table 3−3.
Table 3−3. Integrated Pullup Resistors
SIGNAL NAME
TERMINAL NUMBER
SIGNAL NAME
TERMINAL NUMBER
SIGNAL NAME
PGE GGU GVF
SIGNAL NAME
PGE GGU GVF
A14/CPERR 102 D12 F15 CD2/CCD2 138 B05 C09
A15/CIRDY 110 C10 F13 INPACK/CREQ 122 B08 B12
A19/CBLOCK 101 A13 E18 READY/CINT 131 A06 C10
A20/CSTOP 103 E10 E17 RESET/CRST 119 D08 B13
A21/CDEVSEL 106 D11 A16 VS1/CVS1 130 B02 B10
A22/CTRDY 108 C12 E14 VS2/CVS2 117 A09 F12
BVD1(STSCHG)/CSTSCHG 135 C06 A09 WAIT/CSERR 133 B06 E10
BVD2(SPKR)/CAUDIO 134 D06 F10 WP(IOIS16)/CCLKRUN 136 A05 B09
CD1/CCD1 75 L13 L17
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