2−21
Table 2−13. 16-Bit PC Card Interface Control Terminals
TERMINAL
NUMBER
I/O DESCRIPTION
PGE GGU GVF
BVD1
(STSCHG
/RI)
135 C06 A09
I
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include
batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is
low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the
battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6,
ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,
ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
Status change. STSCHG
is used to alert the system to a change in the READY, write protect,
or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI
is used by 16-bit modem cards to indicate a ring detection.
BVD2(SPKR) 134 D06 F10
I
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include
batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is
low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the
battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6,
ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,
ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
Speaker. SPKR
is an optional binary audio signal available only when the card and socket
have been configured for the 16-bit I/O interface.
CD1
CD2
75
138
L13
B05
L17
C09
I
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC
Card. When a PC Card is inserted into a socket, CD1
and CD2 are pulled low. For signal
status, see Section 5.2, ExCA Interface Status Register.
CE1
CE2
88
90
H13
G13
J15
H17
O
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address
bytes. CE1
enables even-numbered address bytes, and CE2 enables odd-numbered
address bytes.
INPACK 122 B08 B12
I
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read
cycle at the current address.
IORD 94 F12 G18
O
I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data output during
host I/O read cycles.
IOWR 95 C11 G17
O
I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O PC Cards
during host I/O write cycles.
OE 91 G10 H14
O
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data
output during host memory read cycles.
READY
(IREQ
)
131 A06 C10
I
Ready. The ready function is provided by READY when the 16-bit PC Card and the host
socket are configured for the memory-only interface. READY is driven low by the 16-bit
memory PC Cards to indicate that the memory card circuits are busy processing a previous
write command. READY is driven high when the 16-bit memory PC Card is ready to accept a
new data transfer command.
Interrupt request. IREQ
is asserted by a 16-bit I/O PC Card to indicate to the host that a
device on the 16-bit I/O PC Card requires service by the host software. IREQ
is high
(deasserted) when no interrupt is requested.
REG 124 A08 B11
O
Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE
or WE active) and to the I/O space
(IORD
or IOWR active). Attribute memory is a separately accessed section of card memory
and is generally used to record card capacity and other configuration and attribute
information.
RESET 119 D08 B13
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
