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PCA9539PW

Part # PCA9539PW
Description IC DB,DBQ,DGV,DW,PW,RHL,RGE - Rail/Tube
Category IC
Availability Out of Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Philips
Semiconductors
PCA9539
16-bit I
2
C and SMBus, low power I/O port
with interrupt and reset
Product data sheet
Supersedes data of 2004 Aug 27
2004 Sep 30
INTEGRATED CIRCUITS
Philips Semiconductors Product data sheet
PCA9539
16-bit I
2
C and SMBus, low power I/O port
with interrupt and reset
2
2004 Sep 30
FEATURES
16-bit I
2
C GPIO with interrupt and reset
Operating power supply voltage range of 2.3 V–5.5 V
5 V tolerant I/Os
Polarity inversion register
Active LOW interrupt output
Active LOW reset input
Low stand-by current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs
0 kHz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Offered in three different packages: SO24, TSSOP24, and
HVQFN24
DESCRIPTION
The PCA9539 is a 24-pin CMOS device that provide 16 bits of
General Purpose parallel Input/Output (GPIO) expansion with
interrupt and reset for I
2
C/SMBus applications and was developed
to enhance the Philips family of I
2
C I/O expanders. I/O expanders
provides a simple solution when additional I/O is needed for ACPI
power switches, sensors, pushbuttons, LEDs, fans, etc.
The PCA9539 consists of two 8-bit Configuration (Input or Output
selection); Input, Output and Polarity inversion (Active HIGH or
Active LOW operation) registers. The system master can enable the
I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each Input or Output is kept in the corresponding
Input or Output register. The polarity of the read register can be
inverted with the Polarity Inversion Register. All registers can be
read by the system master.
The PCA9539 is identical to the PCA9555 except for the removal of
the internal I/O pull-up resistor which greatly reduces power
consumption when the I/Os are held LOW, repleacement of A2 with
RESET
and different address range.
The PCA9539 open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine. The RESET
pin
causes the same reset/sonfiguration to occur without depowering
the device.
Two hardware pins (A0, A1) vary the fixed I
2
C address and allow up
to four devices to share the same I
2
C/SMBus.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
24-Pin Plastic SO –40 °C to +85 °C PCA9539D PCA9539D SOT137-1
24-Pin Plastic TSSOP –40 °C to +85 °C PCA9539PW PCA9539PW SOT355-1
24-Pin Plastic HVQFN –40 °C to +85 °C PCA9539BS 9539 SOT616-1
Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging.
I
2
C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I
2
C patent.
Philips Semiconductors Product data sheet
PCA9539
16-bit I
2
C and SMBus, low power I/O port
with interrupt and reset
2004 Sep 30
3
PIN CONFIGURATION — SO, TSSOP
SW02200
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
INT
A1
I/O0.0
I/O0.1
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
V
DD
SDA
SCL
A0
I/O1.7
I/O1.6
I/O1.5
I/O1.3
I/O1.4
I/O1.2
I/O1.1
I/O1.0V
SS
RESET
Figure 1. Pin configuration — SO, TSSOP
PIN CONFIGURATION —HVQFN
18
17
16
15
14
7
8
9
10
11
1
2
3
4
5
24
23
22
21
20
SW02201
TOP VIEW
I/O0.0 A0
6
13
12 19
I/O0.1
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O1.3
I/O1.4
I/O1.5
I/O1.6
I/O1.7
I/O0.6
I/O0.7
I/O1.0
I/O1.1
I/O1.2
A1
INT
V
SDA
SCL
DD
V
SS
RESET
Figure 2. Pin configuration — HVQFN
PIN DESCRIPTION
SO, TSSOP
PIN NUMBER
HVQFN
PIN NUMBER
SYMBOL FUNCTION
1 22 INT Interrupt output (open drain)
2 23 A1 Address input 1
3 24 RESET Active LOW reset input
4–11 1–8 I/O0.0–I/O0.7 I/O0.0 to I/O0.7
12 9 V
SS
Supply ground
13–20 10–17 I/O1.0–I/O1.7 I/O1.0 to I/O1.7
21 18 A0 Address input 0
22 19 SCL Serial clock line
23 20 SDA Serial data line
24 21 V
DD
Supply voltage
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