Philips Semiconductors
PCA9517Level translating I
2
C-bus repeater
Product data sheet
2
2004 Oct 05
DESCRIPTION
The PCA9517 is a CMOS integrated circuit that provides level
shifting between low voltage (down to 0.9 V) and higher voltage
(2.7 V to 5.5 V) I
2
C or SMBus applications. While retaining all the
operating modes and features of the I
2
C system during the level
shifts, it also permits extension of the I
2
C-bus by providing
bi-directional buffering for both the data (SDA) and the clock (SCL)
lines, thus enabling two buses of 400 pF. Using the PCA9517
enables the system designer to isolate two halves of a bus for both
voltage and capacitance. The SDA and SCL pins are over voltage
tolerant and are high-impedance when the PCA9517 is unpowered.
The 2.7 V to 5.5 V bus B side drivers behave much like the drivers
on the PCA9515A device while the adjustable voltage bus A side
drivers drive more current and eliminate the static offset voltage.
This results in a LOW on the B side translating into a nearly 0 V
LOW on the A side which accommodates smaller voltage swings of
lower voltage logic.
The static offset design of the B side PCA9517 I/O drivers prevent
them from being connected to another PCA9510, PCA9511, PCA9512,
PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517 (B side), or
PCA9518. The A side of two or more PCA9517s can be connected
together, however, to allow a star topography with the A side on the
common bus, and the A side can be connected directly to any other
buffer with static or dynamic offset voltage. Multiple PCA9517s can
be connected in series, A side to B side, with no build-up in offset
voltage with only time of flight delays to consider.
The PCA9517 drivers are not enabled unless V
CCA
is above 0.8 V
and V
CC
is above 2.5 V. The EN pin can also be used to turn the
drivers on and off under system control. Caution should be observed
to only change the state of the enable pin when the bus is idle.
FEATURES
• 2 channel, bi-directional buffer isolates capacitance and allows
400 pF on either side of the device
• Voltage level translation from 0.9 V to 5.5 V and from
2.7 V to 5.5 V
• Footprint and functions replacement for PCA9515/15A
• I
2
C-bus and SMBus compatible
• Active-HIGH repeater enable input
• Open-drain input/outputs
• Lock-up free operation
• Supports arbitration and clock stretching across the repeater
• Accommodates standard mode and fast mode I
2
C devices and
multiple masters
• Powered-off high-impedance I
2
C pins
• Operating supply voltage range of 2.7 V to 3.6 V
• 5 V tolerant I
2
C and enable pins
• 0 kHz to 400 kHz clock frequency
1
• ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101.
• Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA.
• Packages offered: SO8, TSSOP8 (MSOP8)
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
8-pin plastic SO –40 to +85 °C PCA9517D PCA9517 SOT96-1
8-pin plastic TSSOP (MSOP) –40 to +85 °C PCA9517DP 9517 SOT505-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging/.
PIN CONFIGURATION
1
2
3
4GND
SDAA
SCLB
SDAB
EN5
6
7
8V
CCB
SCLA
SU01790
V
CCA
Figure 1. Pin configuration
PIN DESCRIPTION
PIN SYMBOL FUNCTION
1 V
CCA
A side supply voltage (0.9 V to 5.5 V)
2 SCLA Serial clock A side bus
3 SDAA Serial data A side bus
4 GND Supply ground
5 EN Active-HIGH repeater enable input
6 SDAB Serial data B side bus
7 SCLB Serial clock B side bus
8 V
CCB
B side and device supply voltage
(2.7 V to 3.6 V)
1. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
