ORCA

Series 2

Field-Programmable Gate Arrays

Data Sheet

June 1999

Features

■

High-performance, cost-effective, low-power

0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS

technology (OR2TxxA), and 0.25 µm CMOS technology

(OR2TxxB), (four-input look-up table (LUT) delay less

than 1.0 ns with -8 speed grade)

■

High density (up to 43,200 usable, logic-only gates; or

99,400 gates including RAM)

■

Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are

5 V tolerant to allow interconnection to both 3.3 V and

5 V devices, selectable on a per-pin basis)

■

Four 16-bit look-up tables and four latches/flip-flops per

PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or

32-bit (or wider) bus structures

■

Eight 3-state buffers per PFU for on-chip bus structures

■

Fast, on-chip user SRAM has features to simplify RAM

design and increase RAM speed:

— Asynchronous single port: 64 bits/PFU

— Synchronous single port: 64 bits/PFU

— Synchronous dual port: 32 bits/PFU

■

Improved ability to combine PFUs to create larger RAM

structures using write-port enable and 3-state buffers

■

Fast, dense multipliers can be created with the multiplier

mode (4 x 1 multiplier/PFU):

— 8 x 8 multiplier requires only 16 PFUs

— 30% increase in speed

■

Flip-flop/latch options to allow programmable priority of

synchronous set/reset vs. clock enable

■

Enhanced

cascadable

nibble-wide data path

capabilities for adders, subtractors, counters, multipliers,

and comparators including internal fast-carry operation

■

Innovative, abundant, and hierarchical nibble-

oriented routing resources that allow automatic use of

internal gates for all device densities without sacrificing

performance

■

Upward bit stream compatible with the

ORCA

ATT2Cxx/

ATT2Txx series of devices

■

Pinout-compatible with new

ORCA

Series 3 FPGAs

■

TTL or CMOS input levels programmable per pin for the

OR2CxxA (5 V) devices

■

Individually programmable drive capability:

12 mA sink/6 mA source or 6 mA sink/3 mA source

■

Built-in boundary scan (

IEEE

*1149.1 JTAG) and

3-state all I/O pins, (TS_ALL) testability functions

■

Multiple configuration options, including simple, low pin-

count serial ROMs, and peripheral or JTAG modes for in-

system programming (ISP)

■

Full PCI bus compliance for all devices

■

Supported by industry-standard CAE tools for design

entry, synthesis, and simulation with

ORCA

Foundry

Development System support (for back-end implementa-

tion)

■

New, added features (OR2TxxB) have:

— More I/O per package than the OR2TxxA family

— No dedicated 5 V supply (V

— Faster configuration speed (40 MHz)

— Pin selectable I/O clamping diodes provide 5V or 3.3V

PCI compliance and 5V tolerance

— Full PCI bus compliance in both 5V and 3.3V PCI sys-

tems

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

Table 1

. ORCA

Series 2 FPGAs

* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The

second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of

implementing a 16 x 4 RAM (or 256 gates) per PFU.

Device

Usable

Gates*

# LUTs Registers

Max User

RAM Bits

User

I/Os

Array Size

OR2C04A/OR2T04A 4,800—11,000 400 400 6,400 160 10 x 10

OR2C06A/OR2T06A 6,900—15,900 576 576 9,216 192 12 x 12

OR2C08A/OR2T08A 9,400—21,600 784 724 12,544 224 14 x 14

OR2C10A/OR2T10A 12,300—28,300 1024 1024 16,384 256 16 x 16

OR2C12A/OR2T12A 15,600—35,800 1296 1296 20,736 288 18 x 18

OR2C15A/OR2T15A/OR2T15B 19,200—44,200 1600 1600 25,600 320 20 x 20

OR2C26A/OR2T26A 27,600—63,600 2304 2304 36,864 384 24 x 24

OR2C40A/OR2T40A/OR2T40B 43,200—99,400 3600 3600 57,600 480 30 x 30

Data Sheet

ORCA

Series 2 FPGAs June 1999

2 Lucent Technologies Inc.

Table of Contents

Contents Page Contents Page

Features ......................................................................1

Description...................................................................3

ORCA

Foundry Development System Overview.........5

Architecture .................................................................5

Programmable Logic Cells ..........................................5

Programmable Function Unit...................................5

Look-Up Table Operating Modes ............................7

Latches/Flip-Flops .................................................15

PLC Routing Resources ........................................17

PLC Architectural Description................................22

Programmable Input/Output Cells .............................25

Inputs.....................................................................25

Outputs ..................................................................26

5 V Tolerant I/O (OR2TxxB) ..................................27

PCI Compliant I/O..................................................27

PIC Routing Resources .........................................28

PIC Architectural Description.................................29

PLC-PIC Routing Resources.................................30

Interquad Routing......................................................32

Subquad Routing (OR2C40A/OR2T40A Only)......34

PIC Interquad (MID) Routing .................................36

Programmable Corner Cells......................................37

Programmable Routing..........................................37

Special-Purpose Functions....................................37

Clock Distribution Network ........................................37

Primary Clock ........................................................37

Secondary Clock ...................................................38

Selecting Clock Input Pins.....................................39

FPGA States of Operation.........................................40

Initialization............................................................40

Configuration .........................................................41

Start-Up .................................................................42

Reconfiguration .....................................................42

Partial Reconfiguration ..........................................43

Other Configuration Options..................................43

Configuration Data Format ........................................43

Using

ORCA

Foundry to Generate

Configuration RAM Data.....................................44

Configuration Data Frame .....................................44

Bit Stream Error Checking.........................................47

FPGA Configuration Modes.......................................47

Master Parallel Mode.............................................47

Master Serial Mode ...............................................48

Asynchronous Peripheral Mode ............................49

Synchronous Peripheral Mode ..............................49

Slave Serial Mode .................................................50

Slave Parallel Mode...............................................50

Daisy Chain ...........................................................51

Special Function Blocks ............................................52

Single Function Blocks ..........................................52

Boundary Scan......................................................54

Boundary-Scan Instructions...................................55

ORCA

Boundary-Scan Circuitry ............................56

ORCA

Timing Characteristics....................................60

Estimating Power Dissipation ....................................61

OR2CxxA...............................................................61

OR2TxxA ...............................................................63

OR2T15B and OR2T40B.......................................65

Pin Information ..........................................................66

Pin Descriptions.....................................................66

Package Compatibility ...........................................68

Compatibility with Series 3 FPGAs ........................70

Package Thermal Characteristics............................126

QJA......................................................................126

yJC.......................................................................126

QJC......................................................................126

QJB......................................................................126

Package Coplanarity ...............................................127

Package Parasitics ..................................................127

Absolute Maximum Ratings.....................................129

Recommended Operating Conditions......................129

Electrical Characteristics .........................................130

Timing Characteristics .............................................132

Series 2................................................................160

Measurement Conditions.........................................169

Output Buffer Characteristics...................................170

OR2CxxA.............................................................170

OR2TxxA .............................................................171

OR2TxxB .............................................................172

Package Outline Drawings ......................................173

Terms and Definitions..........................................173

84-Pin PLCC........................................................174

100-Pin TQFP......................................................175

144-Pin TQFP......................................................176

160-Pin QFP........................................................177

208-Pin SQFP......................................................178

208-Pin SQFP2....................................................179

240-Pin SQFP......................................................180

240-Pin SQFP2....................................................181

256-Pin PBGA .....................................................182

304-Pin SQFP......................................................183

304-Pin SQFP2....................................................184

352-Pin PBGA .....................................................185

432-Pin EBGA .....................................................186

Ordering Information................................................187

Index........................................................................189

Data Sheet

June 1999

ORCA

Series 2 FPGAs

Lucent Technologies Inc. 3

Description

The

ORCA

Series 2 series of SRAM-based FPGAs are

an enhanced version of the ATT2C/2T architecture.

The latest

ORCA

series includes patented architectural

enhancements that make functions faster and easier to

design while conserving the use of PLCs and routing

resources.

The Series 2 devices can be used as drop-in replace-

ments for the ATT2Cxx/ATT2Txx series, respectively,

and they are also bit stream compatible with each

other. The usable gate counts associated with each

series are provided in Table 1. Both series are offered

in a variety of packages, speed grades, and tempera-

ture ranges.

The

ORCA

series FPGA consists of two basic ele-

ments: programmable logic cells (PLCs) and program-

mable input/output cells (PICs). An array of PLCs is

surrounded by PICs as shown in Figure 1. Each PLC

contains a programmable function unit (PFU). The

PLCs and PICs also contain routing resources and

configuration RAM. All logic is done in the PFU. Each

PFU contains four 16-bit look-up tables (LUTs) and four

latches/flip-flops (FFs).

The PLC architecture provides a balanced mix of logic

and routing that allows a higher utilized gate/PFU than

alternative architectures. The routing resources carry

logic signals between PFUs and I/O pads. The routing

in the PLC is symmetrical about the horizontal and ver-

tical axes. This improves routability by allowing a bus of

signals to be routed into the PLC from any direction.

Some examples of the resources required and the per-

formance that can be achieved using these devices are

represented in Table 2.

Table 2

. ORCA

Series 2 System Performance

1. Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.

2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.

3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).

4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address

multiplexer.

5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address mul-

tiplexer.

6. Implemented using 16 x 2 synchronous dual-port RAM mode.

7. OR2TxxB available only in -7 and -8 speeds only.

8. Speed grades of -5, -6, and -7 are for OR2TxxA devices only.

Function

PFUs

Speed Grade

Unit

-2A -3A -4A -5A -6A -7A -7B -8B

16-bit loadable up/down

counter

4 51.0 66.7 87.0 104.2

129.9 144.9 131.6 149.3

MHz

16-bit accumulator 4 51.0 66.7 87.0 104.2

129.9 144.9 131.6 149.3

MHz

8 x 8 parallel multiplier:

— Multiplier mode, unpipelined

— ROM mode, unpipelined

— Multiplier mode, pipelined

14.2

41.5

50.5

19.3

55.6

69.0

25.1

71.9

82.0

31.0

87.7

103.1

36.0

107.5

125.0

40.3

122.0

142.9

37.7

103.1

123.5

44.8

120.5

142.9

MHz

32 x 16 RAM:

— Single port (read and write/

cycle)

— Single port

— Dual port

21.8

38.2

28.6

52.6

36.2

69.0

83.3

53.8

92.6

53.8

92.6

62.5

96.2

57.5

97.7

69.4

112.4

MHz

36-bit parity check (internal) 4 13.9 11.0 9.1 7.4

5.6 5.2 6.1 5.1

32-bit address decode

(internal)

3.25 12.3 9.5 7.5 6.1

4.6 4.3 4.8 4.0

Part #	OR2C40A-3PS208I
Description	208 PIN PLASTIC FPGA
Category	IC
Availability	Out of Stock
Qty	0

OR2C40A-3PS208I

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