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OPA2132U

Part # OPA2132U
Description 8 LD SOIC FET OP AMP - Rail/Tube
Category IC
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Burr-Brown Corporation
Date Code: 0102
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

OPA132
,
OPA2132
,
OPA4132
SBOS054B JANUARY 1995REVISED SEPTEMBER 2015
www.ti.com
Pin Functions OPA2132 and OPA4132 (continued)
PIN
I/O DESCRIPTION
OPA2132 OPA4132
NAME
NO. NO.
+In C 10 I Noninverting input channel C
V– 4 11 Negative power supply
+In D 12 I Noninverting input channel D
–In D 13 I Inverting input channel D
Out D 14 O Output channel D
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
Supply voltage, V+ to V– 36 V
Input voltage (V–) –0.7 (V+) +0.7 V
Output short-circuit
(2)
Continuous
Operation temperature –40 125 °C
Junction temperature 150 °C
T
stg
Storage temperature –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE UNIT
OPA132 in PDIP and SOIC Package, OPA2132 and OPA4132 in PDIP Package
V
(ESD)
Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000 V
OPA2132 in SOIC Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
(ESD)
Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-
±500
C101
(2)
OPA4132 in SOIC Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
(ESD)
Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-
±200
C101
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Supply voltage, VS = (V+) (V–) ±2.5 ±15 ±18 V
T
A
Specified temperature range –40 85 °C
4 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: OPA132 OPA2132 OPA4132
OPA132
,
OPA2132
,
OPA4132
www.ti.com
SBOS054B JANUARY 1995REVISED SEPTEMBER 2015
6.4 Electrical Characteristics
At T
A
= 25°C, V
S
= ±15 V, unless otherwise noted.
OPAx132PA, UA
OPAx132P, U
OPA2132PA, UA
OPA2132P, U
PARAMETER TEST CONDITIONS UNIT
OPA4132PA, UA
MIN TYP MAX MIN TYP MAX
OFFSET VOLTAGE
Input Offset Voltage ±0.25 ±0.5 ±0.5 ±2 mV
vs Temperature
(1)
Operating temperature range ±2 ±10 ±2 ±10 µV/°C
vs Power Supply V
S
= ±2.5 V to ±18 V 5 15 5 30 µV/V
Channel Separation (dual and R
L
= 2 kΩ 0.2 0.2
µV/V
quad)
INPUT BIAS CURRENT
Input Bias Current
(2)
V
CM
= 0 V 5 ±50 5 ±50 pA
vs Temperature See Figure 5 See Figure 5
Input Offset Current
(2)
V
CM
= 0 V ±2 ±50 ±2 ±50 pA
NOISE
Input Voltage Noise
f = 10 Hz 23 23
f = 100 H 10 10
Noise Density nV/Hz
f = 1 kHz 8 8
f = 10 kHz 8 8
Current Noise
f = 1 kHz 3 3 fA/Hz
Density,
INPUT VOLTAGE RANGE
(V–) (V+) (V–) (V+)
Common-Mode Voltage Range ±13 ±13 V
+2.5 –2.5 +2.5 –2.5
Common-Mode Rejection V
CM
= 12.5 V to 12.5 V 96 100 86 94 dB
INPUT IMPEDANCE
Differential 10
13
|| 2 10
13
|| 2 Ω || pF
Common-Mode V
CM
= 12.5 V to 12.5 V 10
13
|| 6 10
13
|| 6 Ω || pF
OPEN-LOOP GAIN
R
L
= 10 kΩ, V
O
= –14.5 V 110 120 104 120
to 13.8 V
R
L
= 2 kΩ, V
O
= 13.8 V 110 126 104 120
Open-Loop Voltage Gain dB
to 13.5 V
R
L
= 600 Ω, V
O
= 12.8 V 110 130 104 120
to 12.5 V
FREQUENCY RESPONSE
Gain-Bandwidth Product 8 8 MHz
Slew Rate ±20 ±20 V/µs
G = 1, 10 V Step,
0.1% 0.7 0.7 µs
CL = 100 pF
Settling Time:
G = 1, 10 V Step,
0.01% 1 1 µs
C
L
= 100 pF
Overload Recovery Time G = ± 0.5 0.5 µs
R
L
= 2 kΩ 0.00008% 0.00008%
Total Harmonic Distortion + 1 kHz, G = 1,
Noise V
O
= 3.5 Vrms
R
L
= 600 Ω 0.00009% 0.00009%
(1) Specified by wafer test.
(2) High-speed test at T
J
= 25°C.
Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: OPA132 OPA2132 OPA4132
OPA132
,
OPA2132
,
OPA4132
SBOS054B JANUARY 1995REVISED SEPTEMBER 2015
www.ti.com
Electrical Characteristics (continued)
At T
A
= 25°C, V
S
= ±15 V, unless otherwise noted.
OPAx132PA, UA
OPAx132P, U
OPA2132PA, UA
OPA2132P, U
PARAMETER TEST CONDITIONS UNIT
OPA4132PA, UA
MIN TYP MAX MIN TYP MAX
OUTPUT
(V+) (V+) (V+) (V+)
Positive
–1.2 –0.9 –1.2 –0.9
R
L
= 10 kΩ
(V–) (V–) (V–) (V–)
Negative
+0.5 +0.3 +0.5 +0.3
(V+) (V+) (V+) (V+)
Positive
–1.5 –1.1 –1.5 –1.1
Voltage Output R
L
= 2 kΩ V
(V–) (V–) (V–) (V–)
Negative
+1.2 +0.9 +1.2 +0.9
(V+) (V+) (V+) (V+)
Positive
–2.5 –2.0 –2.5 –2.0
R
L
= 600 Ω
(V–) (V–) (V–) (V–)
Negative
+2.2 +1.5 +2.2 +1.5
Short-Circuit Current ±40 ±40 mA
Capacitive Load Drive (Stable See Figure 17 See Figure 17
Operation)
POWER SUPPLY
Specified Operating Voltage ±15 ±15 V
Operating Voltage Range ±2.5 ±18 ±2.5 ±18 V
Quiescent Current
I
O
= 0 ±4 ±4.8 ±4 ±4.8 mA
(per amplifier)
TEMPERATURE RANGE
Operating Range –40 85 –40 85 °C
Storage –40 125 –40 125 °C
6 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: OPA132 OPA2132 OPA4132
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