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OP497GP

Part # OP497GP
Description OP Amp Quad GP ±20V 14-Pin PDIP - Rail/Tube
Category IC
Availability In Stock
Qty 6
Qty Price
1 - 1 $7.96872
2 - 2 $6.33876
3 - 3 $5.97654
4 - 5 $5.55396
6 + $4.95027
Manufacturer Available Qty
Analog Devices
Date Code: 0449
  • Shipping Freelance Stock: 1
    Ships Immediately
PMI
Date Code: 9502
  • Shipping Freelance Stock: 5
    Ships Immediately

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. D
OP497
–10–
OP497 SPICE MACRO-MODEL
Figure 12 and Table I show the node and net list for a SPICE
macro-model of the OP497. The model is a simplified version of
the actual device and simulates important dc parameters such as
V
OS
, I
OS
, I
B
, A
VO
, CMR, V
O
, and I
SY
. AC parameters such as slew
rate, gain and phase response, and CMR change with frequency
are also simulated by the model.
The model uses typical parameters for the OP497. The poles and
zeros in the model were determined from the actual open and
closed-loop gain and phase response of the OP497. In this way,
the model presents an accurate ac representation of the actual
device. The model assumes an ambient temperature of 25°C.
– +
– +
99
20
21
23
24
25 26
22
R16
D9
G4 G5
D10
G7
L1
V4
V3
G6
D8D7
D5
D6
27
50
I
SY
V
O
R18
R19
R17
G2
R10
CCM
98
ECM
RCM1
RCM2
15 16
C5
19
ⴞ
CNZ
ENZ
RNZ1
RNZ2
17 18
ⴞ
G2
R15
20
C5
–IN
+IN
8
9
7
2
1
C
IN
R1
R2
D1 D2
50
10 11
56
12
98
14
13
G1
C3
V2
C2
Q1 Q2
R6R5
99
V1
E
REF
– +
R
IN2
E
OS
I
1
R
IN1
I
OS
R3 R4
D3
ⴞ
ⴞ
D4
ⴞ
R7
Figure 12. OP497 Macro Model
REV. D
OP497
–11–
* Node assignments
* noninverting input
* inverting input
* positive supply
* negative supply
* output
*
*SUBCKT OP497 1 2 99 50 27
*
* INPUT STAGE AND POLE AT 6 MHz
*
RIN1 1 7 2500
RIN2 2 8 2500
R1 8 3 6.782E8
R2 7 3 6.782E8
R3 5 99 542.57
R4 6 99 542.57
CIN 7 8 3E-12
C2 5 6 24.445E-12
I1 4 50 0.1E-3
IOS 7 8 15E-12
EOS 9 7 POLY(1) 16 21 40E-6 1
Q15810QX
Q26911QX
R5 10 4 25.374
R6 11 4 25.374
D189DX
D298DX
*
EREF 98 0 21 0 1
*
*GAIN STAGE AND DOMINANT POLE AT 0.11 Hz
*
R7 1 98 2.1703E9
C3 2 98 666.67E-12
G1 98 12 5
V1 99 13 1.275
V2 11 9 1.275
D3 12 13 DX
D4 14 12 DX
*
*COMMON-MODE GAIN NETWORK WITH ZERO AT 50 MHz
*
RCM1 15 16 1E6
CCM 15 16 3.18E-9
RCM2 16 98 1
ECM 15 98 3 21 177.83E-3
* NEGATIVE ZERO AT 1.8 MHz
*
E1 17 98 12 21 1E6
R8 17 18 1E6
C4 17 18 –88.419E-15
R9 18 98 1
*
* POLE AT 6 MHz
*
G2 98 19 18 21 1E-6
R15 20 98 1E6
C8 20 98 26.526E-15
*
* POLE AT 1.8 MHz
*
G6 98 20 19 21 1E-6
R20 20 98 1E6
C10 20 98 88.419E-15
*
* OUTPUT STAGE
*
R16 99 21 160 k
R17 21 50 160 k
ISY 99 50 331E-6
V3 23 22 1.9
D5 20 23 DX
V4 22 24 1.9
D6 24 20 DX
D7 99 25 DX
G4 25 50 20 22 5E-3
D9 50 25 DY
D8 99 26 DX
G5 26 50 22 20 5E-3
D10 50 26 DY
G6 22 99 99 20 5E-3
R18 99 22 200
G7 50 22 20 50 5E-3
R19 22 50 200
L1 22 27 0.1E-6
*
* MODELS USED
*
.MODEL QX NPN (BF = 1.25E6)
.MODEL DX (IS = 1E-15)
.MODEL DZ D(IS = 1E-15 BV = 50)
.ENDS OP497
Table I. OP497 SPICE Net-List
–12–
C00309–0–2/02(D)
PRINTED IN U.S.A.
Revision History
Location Page
11/01—Data Sheet changed from REV. C to REV. D.
Edits to PIN CONNECTIONS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Ceramic DIP
(Y-Suffix)
PIN 1
1
14
8
7
0.005 (0.13)
MIN
0.098 (2.49)
MAX
0.310 (7.87)
0.220 (5.59)
0.200 (5.08)
MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MIN
0°–15°
0.015 (0.38)
0.008 (0.20)
0.320 (8.13)
0.290 (7.37)
0.785 (19.94) MAX
SEATING PLANE
14-Lead Epoxy DIP
(P-Suffix)
PIN 1
1
14
8
7
0.325 (8.25)
0.300 (7.62)
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.92) 0.022 (0.558)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
0°–15°
0.015 (0.38)
0.008 (0.20)
0.280 (7.11)
0.240 (6.10)
0.015 (0.381)
MIN
0.795 (20.19)
0.725 (18.41)
16-Lead Wide-Body SOIC
(S-Suffix)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.050 (1.27)
BSC
16 9
81
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4133 (10.50)
0.3977 (10.00)
0.0125 (0.32)
0.0091 (0.23)
8ⴗ
0ⴗ
0.0291 (0.74)
0.0098 (0.25)
ⴛ 45ⴗ
0.0500 (1.27)
0.0157 (0.40)
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