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OP482GP

Part # OP482GP
Description OP Amp Quad GP ±18V 14-Pin PDIP N
Category IC
Availability In Stock
Qty 16
Qty Price
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4 - 6 $3.49789
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14 + $2.73168
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Analog Devices
Date Code: 0014
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Dual/Quad Low Power, High Speed
JFET Operational Amplifiers
OP282/OP482
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. Slew rate
exceeds 7 V/µs with supply current under 250 µA per amplifier.
These unity gain stable amplifiers have a typical gain bandwidth
of 4 MHz.
The JFET input stage of the OP282/OP482 insures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 volts of each supply, low
power consumption and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power restricted applica-
tions. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for high-
side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. Both dual and quad amplifiers are available
in plastic and ceramic DIP plus SOIC surface mount packages.
FEATURES
High Slew Rate: 9 V/ms
Wide Bandwidth: 4 MHz
Low Supply Current: 250 mA/Amplifier
Low Offset Voltage: 3 mV
Low Bias Current: 100 pA
Fast Settling Time
Common-Mode Range Includes V+
Unity Gain Stable
APPLICATIONS
Active Filters
Fast Amplifiers
Integrators
Supply Current Monitoring
PIN CONNECTIONS
8-Lead Narrow-Body SOIC 8-Lead Epoxy DIP
(S Suffix) (P Suffix)
1
2
3
45
6
7
8
OUT A
–IN A
+IN A
V–
OP-482
V+
OUT B
–IN B
+IN B
OP282
OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
1
2
3
4
5
6
7
8
OP282
14-Lead Epoxy DIP 14-Lead Narrow-Body SOIC
(P Suffix) (S Suffix)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT B
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP482
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP482
–2–
OP282/OP482–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V
S
= 615.0 V, T
A
= +258C unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Units
INPUT CHARACTERISTICS
Offset Voltage V
OS
OP282 0.2 3 mV
OP282, –40 ≤ T
A
≤ +85°C 4.5 mV
Offset Voltage V
OS
OP482 0.2 4 mV
OP482, –40 ≤ T
A
≤ +85°C6mV
Input Bias Current I
B
V
CM
= 0 V 3 100 pA
V
CM
= 0 V, Note 1 500 pA
Input Offset Current I
OS
V
CM
= 0 V 1 50 pA
V
CM
= 0 V, Note 1 250 pA
Input Voltage Range –11 +15 V
Common-Mode Rejection CMR –11 V ≤ V
CM
≤ +15 V, –40 ≤ T
A
≤ +85°C7090 dB
Large Signal Voltage Gain A
VO
R
L
= 10 kΩ 20 V/mV
R
L
= 10 kΩ, –40 ≤ T
A
≤ +85°C 15 V/mV
Offset Voltage Drift ∆V
OS
/∆T10µV/°C
Bias Current Drift ∆I
B
/∆T 8 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing V
O
R
L
= 10 kΩ –13.5 ±13.9 13.5 V
Short Circuit Limit I
SC
Source 3 10 mA
Sink –8 –12 mA
Open-Loop Output Impedance Z
OUT
f = 1 MHz 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR V
S
= ±4.5 V to ± 18 V,
–40 ≤ T
A
≤ +85°C 25 316 µV/V
Supply Current/Amplifier I
SY
V
O
= 0 V, 40 ≤ T
A
≤ +85°C 210 250 µA
Supply Voltage Range V
S
±4.5 ±18 V
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 10 kΩ 79 V/µs
Full-Power Bandwidth BW
P
1% Distortion 125 kHz
Settling Time t
S
To 0.01% 1.6 µs
Gain Bandwidth Product GBP 4 MHz
Phase Margin Ø
O
55 Degrees
NOISE PERFORMANCE
Voltage Noise e
n
p-p 0.1 Hz to 10 Hz 1.3 µV p-p
Voltage Noise Density e
n
f = 1 kHz 36 nV/√Hz
Current Noise Density i
n
0.01 pA/√Hz
NOTE
1
The input bias and offset currents are tested at T
A
= T
J
= +85°C. Bias and offset currents are guaranteed but not tested at –40°C.
Specifications subject to change without notice.
WAFER TEST LIMITS
(@ V
S
= 615.0 V, T
A
= +258C unless otherwise noted)
Parameter Symbol Conditions Limit Units
Offset Voltage V
OS
OP282 3 mV max
Offset Voltage V
OS
OP482 4 mV max
Input Bias Current I
B
V
CM
= 0 V 100 pA max
Input Offset Current I
OS
V
CM
= 0 V 50 pA max
Input Voltage Range
1
–11, +15 V min/max
Common-Mode Rejection CMRR –11 V ≤ V
CM
≤ +15 V 70 dB min
Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 316 µV/V
Large Signal Voltage Gain A
VO
R
L
= 10 kΩ 20 V/mV min
Output Voltage Range V
O
R
L
= 10 kΩ±13.5 V min
Supply Current/Amplifier I
SY
V
O
= 0 V, R
L
= ∞ 250 µA max
NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1
Guaranteed by CMR test.
Specifications subject to change without notice.
REV. B
OP282/OP482
REV. B
–3–
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP282A, OP482A . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP282G, OP482G . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C
Package Type u
JA
2
u
JC
Units
8-Pin Plastic DIP (P) 103 43 °C/W
8-Pin SOIC (S) 158 43 °C/W
14-Pin Plastic DIP (P) 83 39 °C/W
14-Pin SOIC (S) 120 36 °C/W
NOTES
1
For supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
2
θ
JA
is specified for the worst case conditions, i.e., θ
JA
is specified for device in
socket for cerdip, P-DIP; θ
JA
is specified for device soldered in circuit board for
SOIC package.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
OP282GP –40°C to +85°C 8-Pin Plastic DIP N-8
OP282GS –40°C to +85°C 8-Pin SOIC SO-8
OP482GP –40°C to +85°C 14-Pin Plastic DIP N-14
OP482GS –40°C to +85°C 14-Pin SOIC SO-14
DICE CHARACTERISTICS
OP282 Die Size 0.063
3
0.060 Inch, 3,780 Sq. Mils
OP482 Die Size 0.070
3
0.098 Inch, 6,860 Sq. Mils
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