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MT8888CE

Part # MT8888CE
Description DTMF TXRX 3.58MHz CMOS 5V 20-Pin PDIP Tube
Category IC
Availability Out of Stock
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1 + $8.28410



Technical Document


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4-91
Features
Central office quality DTMF transmitter/receiver
Low power consumption
High speed Intel micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8888C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT8888C utilizes an Intel micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
The MT8888C-1 is functionally identical to the
MT8888C except the receiver is enhanced to accept
lower level signals, and also has a specified low
signal rejection level.
Ordering Information
MT8888CE/CE-1 20 Pin Plastic DIP
MT8888CC/CC-1 20 Pin Ceramic DIP
MT8888CS/CS-1 20 Pin SOIC
MT8888CN/CN-1 24 Pin SSOP
-40°C to +85°C
Figure 1 - Functional Block Diagram
TONE
IN+
IN-
GS
OSC1
OSC2
V
DD
V
Ref
V
SS
ESt St/GT
D0
D1
D2
D3
IRQ
/CP
RD
CS
R/W
RS0
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Data
Bus
Buffer
Tone Burst
Gating Cct.
+
-
Oscillator
Circuit
Bias
Circuit
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Logic
Steering
Logic
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
Interrupt
Logic
I/O
Control
Low Group
Filter
High Group
Filter
Dial
Tone
Filter
ISSUE 2 May 1995
MT8888C/MT8888C-1
Integrated DTMF Transceiver
with Intel Micro Interface
MT8888C/MT8888C-1
4-92
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
20 24
11 IN+Non-inverting op-amp input.
22 IN-Inverting op-amp input.
33 GSGain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
44V
Ref
Reference Voltage output (V
DD
/2).
55 V
SS
Ground (0V).
66OSC1Oscillator input. This pin can also be driven directly by an external clock.
77OSC2Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
8 10 TONE Output from internal DTMF transmitter.
911 WR
Write microprocessor input. TTL compatible.
10 12 CS
Chip Select input. Active Low. This signal must be qualified externally by address latch
enable (ALE) signal, see Figure 12.
11 13 RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
12 14 RD
Read microprocessor input. TTL compatible.
13 15 IRQ
/
CP
Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
14-
17
18-
21
D0-D3 Microprocessor Data Bus. High impedance when CS
= 1 or RD = 1.
TTL compatible.
18 22 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19 23 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V
TSt
detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 V
DD
Positive power supply (5V typ.).
8,9
16,17
NC No Connection.
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ
/CP
RD
RS0
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ
/CP
RD
RS0
24 PIN SSOP
20 PIN CERDIP/PLASTIC DIP/SOIC
MT8888C/MT8888C-1
4-93
Functional Description
The MT8888C/MT8888C-1 Integrated DTMF
Transceiver consists of a high performance DTMF
receiver with an internal gain setting amplifier and a
DTMF generator which employs a burst counter to
synthesize precise tone bursts and pauses. A call
progress mode can be selected so that frequencies
within the specified passband can be detected. The
Intel micro interface allows microcontrollers, such as
the 8080, 80C31/51 and 8085, to access the
MT8888C/MT8888C-1 internal registers.
Input Configuration
The input arrangement of the MT8888C/MT8888C-1
provides a differential-input operational amplifier as
well as a bias source (V
Ref
), which is used to bias the
inputs at V
DD
/2. Provision is made for connection of
a feedback resistor to the op-amp output (GS) for
gain adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
Figure 4 shows the necessary connections for a
differential input configuration.
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). These
filters incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
Figure 3 - Single-Ended Input Configuration
C
R
IN
R
F
IN+
IN-
GS
V
Ref
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
MT8888C/
MT8888C-1
Figure 4 - Differential Input Configuration
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
F
LOW
F
HIGH
DIGIT D
3
D
2
D
1
D
0
697 1209 1 0 0 0 1
697 1336 2 0 0 1 0
697 1477 3 0 0 1 1
770 1209 4 0 1 0 0
770 1336 5 0 1 0 1
770 1477 6 0 1 1 0
852 1209 7 0 1 1 1
852 1336 8 1 0 0 0
852 1477 9 1 0 0 1
941 1336 0 1 0 1 0
941 1209 * 1 0 1 1
941 1477 # 1 1 0 0
697 1633 A 1 1 0 1
770 1633 B 1 1 1 0
852 1633 C 1 1 1 1
941 1633 D 0 0 0 0
C1
C2
R1
R2
R3
R4
R5
IN+
IN-
GS
V
Ref
MT8888C/
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 k
R2 = 60k, R3 = 37.5 k
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
V
diff) - R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2 R1
2
+ (1/ωC)
2
MT8888C-1
123456NEXT