Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14555B/D
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary–to–hexadecimal (1–of–16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
• Diode Protection on All Inputs
• Active High or Active Low Outputs
• Expandable
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation,
per Package (Note 3.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
) V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
X = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14555BCP PDIP–16 2000/Box
MC14555BD SOIC–16 48/Rail
MC14555BDR2 SOIC–16 2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC1455XBCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
1455XB
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC1455XB
AWLYWW
MC14555BFEL SOEIAJ–16 See Note 1.
MC14555BF SOEIAJ–16 See Note 1.
MC14556BCP PDIP–16 2000/Box
MC14556BD SOIC–16 48/Rail
MC14556BDR2 SOIC–16 2500/Tape & Reel
MC14556BFEL SOEIAJ–16 See Note 1.
MC14556BF SOEIAJ–16 See Note 1.
