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MC10216L

Part # MC10216L
Description Triple Receiver 16-Pin CDIP Rail
Category IC
Availability In Stock
Qty 4
Qty Price
1 + $4.63843
Manufacturer Available Qty
Motorola Corp
Date Code: 8522
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1 Publication Order Number:
MC10216/D
MC10216
High Speed Triple Line
Receiver
The MC10216 is a high speed triple differential amplifier designed
for use in sensing differential signals over long lines. The base bias
supply (V
BB
) is made available at pin 11 to make the device useful as a
Schmitt trigger, or in other applications where a stable reference
voltage is necessary.
Active current sources provide the MC10216 with excellent
common mode noise rejection. If any amplifier in a package is not
used, one input of that amplifier must be connected to V
BB
(pin 11) to
prevent upsetting the current source bias network.
Complementary outputs are provided to allow driving twisted pair
lines, to enable cascading of several amplifiers in a chain, or simply to
provide complement outputs of the input logic function.
P
D
= 100 mW typ/pkg (No Load)
t
pd
= 1.8 ns typ (Single ended)
= 1.5 ns typ (Differential)
t
r
, t
f
= 1.5 ns typ (20%–80%)
DIP PIN ASSIGNMENT
V
CC1
A
OUT
A
OUT
A
IN
A
IN
B
OUT
B
OUT
V
EE
V
CC2
C
OUT
C
OUT
C
IN
C
IN
V
BB
B
IN
B
IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
5
4
11
3
2
10
9
7
6
13
12
15
14
V
BB
*V
BB
to be used to supply bias to the MC10216 only and
bypassed (when used) with 0.01
µF to 0.1 µF capacitor.
When the input pin with bubble goes positive, it’s
respective output pin with bubble goes positive.
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Device Package Shipping
ORDERING INFORMATION
MC10216L CDIP–16 25 Units / Rail
MC10216P PDIP–16 25 Units / Rail
MC10216FN PLCC–20 46 Units / Rail
MARKING
DIAGRAMS
1
16
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10216L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10216
AWLYYWW
1
1
16
MC10216P
AWLYYWW
MC10216
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2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
U
n
d
er
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 27 20 25 27 mAdc
Input Current I
inH
4 180 115 115 µAdc
I
CBO
4
9
1.5
1.5
1.0
1.0
1.0
1.0
µAdc
Output Voltage Logic 1 V
OH
2
3
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage Logic 0 V
OL
2
3
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage Logic 1 V
OHA
2
3
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
2
3
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Reference Voltage V
BB
11 –1.420 –1.280 –1.350 –1.230 –1.295 –1.150 Vdc
Switching Times (50 Load) ns
Propagation Delay t
4+2+
t
4–2–
t
4+3–
t
4–3+
2
2
3
3
1.0
1.0
1.0
1.0
2.6
2.6
2.6
2.6
1.0
1.0
1.0
1.0
1.8*
1.8*
1.8*
1.8*
2.5
2.5
2.5
2.5
1.0
1.0
1.0
1.0
2.8
2.8
2.8
2.8
Rise Time (20 to 80%) t
2+
t
3+
2
3
1.0
1.0
2.6
2.6
1.0
1.0
1.5
1.5
2.5
2.5
1.0
1.0
2.8
2.8
Fall Time (20 to 80%) t
2–
t
3–
2
3
1.0
1.0
2.6
2.6
1.0
1.0
1.5
1.5
2.5
2.5
1.0
1.0
2.8
2.8
* Delay is 1.5ns when inputs are driven differentially.
Delay is 1.8ns when inputs are driven single ended.
MC10216
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3
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
BB
V
EE
–30°C –0.890 –1.890 –1.205 –1.500
From
–5.2
+25°C –0.810 –1.850 –1.105 –1.475
F
rom
Pin
–5.2
+85°C –0.700 –1.825 –1.035 –1.440
Pin
11
–5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V )
Characteristic Symbol
Under
Test
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
BB
V
EE
(V
CC
)
Gnd
Power Supply Drain Current I
E
8 4, 9, 12 5, 10, 13 8 1, 16
Input Current I
inH
4 4 9, 12 5, 10, 13 8 1, 16
I
CBO
4
9
9, 12
4, 12
5, 10, 13
5, 10, 13
8, 4
8, 9
1, 16
Output Voltage Logic 1 V
OH
2
3
4
9, 12
9, 12
4
5, 10, 13
5, 10, 13
8
8
1, 16
1, 16
Output Voltage Logic 0 V
OL
2
3
9, 12
4
4
9, 12
5, 10, 13
5, 10, 13
8
8
1, 16
1, 16
Threshold Voltage Logic 1 V
OHA
2
3
9, 12
9, 12 4
4
5, 10, 13
5, 10, 13
8
8
1, 16
1, 16
Threshold Voltage Logic 0 V
OLA
2
3
9, 12
9, 12
4
4 5, 10, 13
5, 10, 13
8
8
1, 16
1, 16
Reference Voltage V
BB
11 5, 10, 13 8 1, 16
Switching Times (50 Load) Pulse In
Pulse Out
–3.2 V +2.0 V
Propagation Delay t
4+2+
t
4–2–
t
4+3–
t
4–3+
2
2
3
3
4
4
4
4
2
2
3
3
5, 10, 13
5, 10, 13
5, 10, 13
5, 10, 13
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Rise Time (20 to 80%) t
2+
t
3+
2
3
4
4
2
3
5, 10, 13
5, 10, 13
8
8
1, 16
1, 16
Fall Time (20 to 80%) t
2–
t
3–
2
3
4
4
2
3
5, 10, 13
5, 10, 13
8
8
1, 16
1, 16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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