MAX1204

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

16 ______________________________________________________________________________________

shut down the converter completely. SHDN overrides

bits 1 and 0 of the control byte.

Full power-down mode turns off all chip functions

that draw quiescent current, reducing I

and I

typi-

cally to 2µA.

Fast power-down mode turns off all circuitry except the

bandgap reference. With fast power-down mode, the

supply current is 30µA. Power-up time can be shortened

to 5µs in internal compensation mode.

The I

shutdown current can increase if any digital input

(DIN, SCLK, CS) is held high in either power-down mode.

The actual shutdown current depends on the state of the

digital inputs, the voltage applied to the digital inputs

), the supply voltage (V

), and the operating temper-

ature. Figure 12c shows the maximum I

increase for

each digital input held high in power-down mode for differ-

ent operating conditions. This current is cumulative, so if

all three digital inputs are held high, the additional shut-

down current is three times the value shown in Figure 12c.

In both software power-down modes, the serial interface

remains operational, but the ADC does not convert.

Table 5 shows how the choice of reference-buffer com-

pensation and power-down mode affects both power-up

delay and maximum sample rate.

In external compensation mode, power-up time is 20ms

with a 4.7µF compensation capacitor (200ms with a 33µF

capacitor) when the capacitor is initially fully discharged.

From fast power-down, start-up time can be eliminated

by using low-leakage capacitors that do not discharge

more than 1/2LSB while shut down. In power-down, the

capacitor has to supply the current into the reference

(typically 1.5µA) and the transient currents at power-up.

Figures 12a and 12b show the various power-down

sequences in both external and internal clock modes.

Software Power-Down

Software power-down is activated using bits PD1 and

PD0 of the control byte. As shown in Table 6, PD1 and

PD0 also specify clock mode. When software power-

down is asserted, the ADC continues to operate in the

last specified clock mode until the conversion is com-

plete. The ADC then powers down into a low

quiescent-current state. In internal clock mode, the

interface remains active and conversion results can be

clocked out even though the MAX1204 has already

entered a software power-down.

The first logical 1 on DIN is interpreted as a start bit

and powers up the MAX1204. Following the start bit,

the control byte also determines clock and power-down

modes. For example, if the control byte contains PD1 =

1, the chip remains powered up. If PD1 = 0,

power-down resumes after one conversion.

Table 5. Typical Power-Up Delay Times

1332FullDisabled

1332FastDisabled

133

MAXIMUM

SAMPLING RATE

(ksps)

See Figure 14c

300

POWER-UP

DELAY (µs)

Fast/Full

Full

Fast

POWER-DOWN

MODE

4.7

REFERENCE

CAPACITOR

(µF)

ExternalEnabled

REFERENCE

BUFFER

InternalEnabled

REFERENCE-BUFFER

COMPENSATION MODE

Full power-down mode00

Fast power-down mode10

PD1

Internal clock mode01

External clock mode11

DEVICE MODEPD0

N/A

Full

Power-Down

GND

STATE

External compensationEnabledFloating

Internal compensationEnabledV

REFERENCE-BUFFER

COMPENSATION

DEVICE

MODE

Table 6. Software Shutdown and

Clock Mode

Table 7. Hard-Wired Shutdown and

Compensation Mode

MAX1204

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

______________________________________________________________________________________ 17

Hardware Power-Down

The SHDN pin places the converter into full

power-down mode. Unlike the software power-down

modes, conversion is not completed; it stops coinci-

dentally with SHDN being brought low. There is no

power-up delay if an external reference, which is not

shut down, is used. SHDN also selects internal or

external reference compensation (Table 7).

Power-Down Sequencing

The MAX1204’s automatic power-down modes can

save considerable power when operating at less than

maximum sample rates. The following sections discuss

the various power-down sequences.

Lowest Power at up to

500 Conversions per Channel per Second

Figure 14a depicts MAX1204’s power consumption for one

or eight channel conversions using full power-down mode

and internal reference compensation. A 0.01µF bypass

capacitor at REFADJ forms an RC filter with the internal

20kΩ reference resistor, with a 0.2ms time constant. To

achieve full 10-bit accuracy, 10 time constants (or 2ms in

this example) are required for the reference buffer to settle.

When exiting FULLPD, waiting this 2ms in FASTPD mode

(instead of just exiting FULLPD mode and returning to nor-

mal operating mode) reduces power consumption by a

factor of 10 or more (Figure 13).

Figure 12b. Timing Diagram for Power-Down Modes (Internal Clock)

FULL

POWER-DOWN

POWERED

POWERED UP

DATA VALID

INTERNAL CLOCK MODE

XXXX

10 S 00

XXXXX 

MODE

DOUT

DIN

CLOCK

MODE

SETS INTERNAL

CLOCK MODE

SETS FULL

POWER-DOWN

CONVERSION

SSTRB

Figure 12a. Timing Diagram for Power-Down Modes (External Clock)

POWERED UP

FULL

POWER-

DOWN

POWERED

POWERED UP

DATA VALID

(10 + 2 DATA BITS)

DATA VALID

(10 + 2 DATA BITS)

DATA 

INVALID



EXTERNAL

INTERNAL

XXXX

11 S 01

XXXXX XXXXX

S11

FAST

POWER-DOWN

MODE

DOUT

DIN

CLOCK

MODE

SHDN

SETS EXTERNAL

CLOCK MODE

SETS EXTERNAL

CLOCK MODE

SETS FAST

POWER-DOWN 

MODE

MAX1204

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

18 ______________________________________________________________________________________

Lowest Power at Higher Throughputs

Figure 14b shows power consumption with external-

reference compensation in fast power-down, with one and

eight channels converted. The external 4.7µF compensa-

tion requires a 50µs wait after power-up. This circuit com-

bines fast multichannel conversion with the lowest power

consumption possible. Full power-down mode can

increase power savings in applications where the

MAX1204 is inactive for long periods of time, but where

intermittent bursts of high-speed conversions are required.

External and Internal References

The MAX1204 can be used with an internal or external

reference. An external reference can be connected

directly at the REF terminal or at the REFADJ pin.

An internal buffer is designed to provide 4.096V at REF

for the MAX1204. Its internally trimmed 2.44V reference

is buffered with a 1.68 nominal gain.

Internal Reference

The MAX1204’s full-scale range with internal reference is

4.096V with unipolar inputs and ±2.048V with bipolar

inputs. The internal reference voltage is adjustable to

±1.5% with the circuit of Figure 17.

External Reference

An external reference can be placed at either the input

(REFADJ) or the output (REF) of the MAX1204’s internal

buffer amplifier. The REFADJ input impedance is typical-

ly 20kΩ. At REF, the input impedance is a minimum of

12kΩ for DC currents. During conversion, an external

reference at REF must deliver up to 350µA DC load cur-

rent and have an output impedance of 10Ω or less. If the

reference has higher output impedance or is noisy,

bypass it close to the REF pin with a 4.7µF capacitor.

Using the buffered REFADJ input makes buffering of

the external reference unnecessary. To use the direct

REF input, disable the internal buffer by tying REFADJ

to V

. In power-down, the input bias current to

REFADJ can be as much as 25µA with REFADJ tied to

. Pull REFADJ to GND to minimize the input bias

current in power-down.

Transfer Function and Gain Adjust

Figure 15 depicts the nominal, unipolar input/output

(I/O) transfer function, and Figure 16 shows the bipolar

I/O transfer function. Code transitions occur halfway

between successive integer LSB values. Output coding

is binary with 1 LSB = 4mV (4.096V/1024) for

unipolar operation and 1 LSB = 4mV [(4.096V/2 -

-4.096V/2)/1024] for bipolar operation.

Figure 13. MAX1204 FULLPD/FASTPD Power-Up Sequence

100

DIN

REFADJ

REF

2.5V

101 1 11100 101

FULLPD FASTPD NOPD FULLPD FASTPD

2ms WAIT

COMPLETE CONVERSION SEQUENCE

BUFFEN

≈ 15µs

τ = RC = 20kΩ x C

REFADJ

(ZEROS)

CH1 CH7

(ZEROS)

Figure 12c. Additional I

Shutdown Supply Current vs. V

for Each Digital Input at a Logic 1

-60

TEMPERATURE (°C)

SUPPLY CURRENT PER INPUT (µA)

100

-20 60 140



- V

) = 1.95V

- V

) = 2.55V

- V

) = 2.25V

Part #	MAX1204BCAP
Description	IC ADC 8CH 10BIT 133KHZ 20-SSOP
Category	IC
Availability	In Stock
Qty	1

MAX1204BCAP

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