15
LT1166
SCHEMATIC
WW
SI PLIFIED
V
AB
+
V
AB
–
1k
1k
R1
200Ω
R2
200Ω
8
7
1
3
2
5
6
4
Q7
× 10
Q8
× 10
Q9
× 1
Q10
× 1
–
+
–
+
Q11
Q12
Q1
Q2
I
REF
I
REF
10
SHUNT
REGULATOR
1166 • SS
Q4
× 32
Q3
× 1
Q6
× 32
Q5
× 1
V
TOP
SENSE
+
V
BOTTOM
SENSE
–
I
LIM
–
V
OUT
I
LIM
+
V
IN
N8 0695
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.015
(0.380)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
12
3
4
876
5
0.255 ± 0.015*
(6.477 ± 0.381)
0.400*
(10.160)
MAX
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325
+0.025
–0.015
+0.635
–0.381
8.255
()
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
U
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
