Figure 15-10. Master Burst RECEIVE .................................................................................................. 382

Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383

Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384

Figure 15-13. Slave Command Sequence ............................................................................................ 385

Figure 16-1. Ethernet Controller Block Diagram .................................................................................. 410

Figure 16-2. Ethernet Controller ......................................................................................................... 410

Figure 16-3. Ethernet Frame ............................................................................................................. 412

Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 453

Figure 17-2. Structure of Comparator Unit .......................................................................................... 454

Figure 17-3. Comparator Internal Reference Structure ........................................................................ 455

Figure 18-1. PWM Module Block Diagram .......................................................................................... 465

Figure 18-2. PWM Count-Down Mode ................................................................................................ 466

Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 467

Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 467

Figure 18-5. PWM Dead-Band Generator ........................................................................................... 468

Figure 19-1. QEI Block Diagram ........................................................................................................ 502

Figure 19-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 503

Figure 20-1. Pin Connection Diagram ................................................................................................ 518

Figure 23-1. Load Conditions ............................................................................................................ 538

Figure 23-2. I

C Timing ..................................................................................................................... 541

Figure 23-3. External XTLP Oscillator Characteristics ......................................................................... 543

Figure 23-4. Hibernation Module Timing ............................................................................................. 544

Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 545

Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 545

Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 546

Figure 23-8. JTAG Test Clock Input Timing ......................................................................................... 547

Figure 23-9. JTAG Test Access Port (TAP) Timing .............................................................................. 547

Figure 23-10. JTAG TRST Timing ........................................................................................................ 547

Figure 23-11. External Reset Timing (RST) .......................................................................................... 548

Figure 23-12. Power-On Reset Timing ................................................................................................. 549

Figure 23-13. Brown-Out Reset Timing ................................................................................................ 549

Figure 23-14. Software Reset Timing ................................................................................................... 549

Figure 23-15. Watchdog Reset Timing ................................................................................................. 549

Figure 24-1. 100-Pin LQFP Package .................................................................................................. 550

November 30, 200710

Preliminary

Table of Contents

List of Tables

Table 1. Documentation Conventions ............................................................................................ 20

Table 3-1. Memory Map ................................................................................................................... 43

Table 4-1. Exception Types .............................................................................................................. 45

Table 4-2. Interrupts ........................................................................................................................ 46

Table 5-1. JTAG Port Pins Reset State ............................................................................................. 50

Table 5-2. JTAG Instruction Register Commands ............................................................................... 55

Table 6-1. System Control Register Map ........................................................................................... 65

Table 7-1. Hibernation Module Register Map ................................................................................... 125

Table 8-1. Flash Protection Policy Combinations ............................................................................. 141

Table 8-2. Flash Resident Registers ............................................................................................... 142

Table 8-3. Flash Register Map ........................................................................................................ 142

Table 9-1. GPIO Pad Configuration Examples ................................................................................. 167

Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 167

Table 9-3. GPIO Register Map ....................................................................................................... 168

Table 10-1. Available CCP Pins ........................................................................................................ 205

Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208

Table 10-3. Timers Register Map ...................................................................................................... 214

Table 11-1. Watchdog Timer Register Map ........................................................................................ 241

Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264

Table 12-2. ADC Register Map ......................................................................................................... 268

Table 13-1. UART Register Map ....................................................................................................... 302

Table 14-1. SSI Register Map .......................................................................................................... 347

Table 15-1. Examples of I

C Master Timer Period versus Speed Mode ............................................... 377

Table 15-2. Inter-Integrated Circuit (I

C) Interface Register Map ......................................................... 386

Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391

Table 16-1. TX & RX FIFO Organization ........................................................................................... 413

Table 16-2. Ethernet Register Map ................................................................................................... 416

Table 17-1. Comparator 0 Operating Modes ...................................................................................... 454

Table 17-2. Comparator 1 Operating Modes ..................................................................................... 455

Table 17-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 455

Table 17-4. Analog Comparators Register Map ................................................................................. 457

Table 18-1. PWM Register Map ........................................................................................................ 470

Table 19-1. QEI Register Map .......................................................................................................... 505

Table 21-1. Signals by Pin Number ................................................................................................... 519

Table 21-2. Signals by Signal Name ................................................................................................. 523

Table 21-3. Signals by Function, Except for GPIO ............................................................................. 528

Table 21-4. GPIO Pins and Alternate Functions ................................................................................. 532

Table 22-1. Temperature Characteristics ........................................................................................... 534

Table 22-2. Thermal Characteristics ................................................................................................. 534

Table 23-1. Maximum Ratings .......................................................................................................... 535

Table 23-2. Recommended DC Operating Conditions ........................................................................ 535

Table 23-3. LDO Regulator Characteristics ....................................................................................... 536

Table 23-4. Detailed Power Specifications ........................................................................................ 537

Table 23-5. Flash Memory Characteristics ........................................................................................ 538

Table 23-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 538

Table 23-7. Clock Characteristics ..................................................................................................... 538

11November 30, 2007

Preliminary

LM3S6965 Microcontroller

Table 23-8. Crystal Characteristics ................................................................................................... 539

Table 23-9. ADC Characteristics ....................................................................................................... 539

Table 23-10. Analog Comparator Characteristics ................................................................................. 540

Table 23-11. Analog Comparator Voltage Reference Characteristics .................................................... 540

Table 23-12. I

C Characteristics ......................................................................................................... 540

Table 23-13. 100BASE-TX Transmitter Characteristics ........................................................................ 541

Table 23-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 541

Table 23-15. 100BASE-TX Receiver Characteristics ............................................................................ 541

Table 23-16. 10BASE-T Transmitter Characteristics ............................................................................ 541

Table 23-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 542

Table 23-18. 10BASE-T Receiver Characteristics ................................................................................ 542

Table 23-19. Isolation Transformers ................................................................................................... 542

Table 23-20. Ethernet Reference Crystal ............................................................................................ 543

Table 23-21. External XTLP Oscillator Characteristics ......................................................................... 543

Table 23-22. Hibernation Module Characteristics ................................................................................. 544

Table 23-23. SSI Characteristics ........................................................................................................ 544

Table 23-24. JTAG Characteristics ..................................................................................................... 546

Table 23-25. GPIO Characteristics ..................................................................................................... 548

Table 23-26. Reset Characteristics ..................................................................................................... 548

Table C-1. Part Ordering Information ............................................................................................... 577

November 30, 200712

Preliminary

Table of Contents

Part #	LM3S6965-IQC50
Description	MCU 32-bit ARM FLASH256KB 2.5V/3V/3.3V 100P LQFP
Category	IC
Availability	Out of Stock
Qty	0

LM3S6965-IQC50

Related Items

Technical Document