Name: LM1881N
SKU: LM1881N
Price: 1.14181 USD
Availability: InStock

LM1881

www.ti.com

SNLS384F –FEBRUARY 1995–REVISED MARCH 2013

LM1881 Video Sync Separator

Check for Samples: LM1881

FEATURES

DESCRIPTION

The LM1881 Video sync separator extracts timing

• AC Coupled Composite Input Signal

information including composite and vertical sync,

• >10 kΩ Input Resistance

burst/back porch timing, and odd/even field

• <10 mA Power Supply Drain Current

information from standard negative going sync NTSC,

PAL

(1)

and SECAM video signals with amplitude from

• Composite Sync and Vertical Outputs

0.5V to 2V p-p. The integrated circuit is also capable

• Odd/Even Field Output

of providing sync separation for non-standard, faster

• Burst Gate/Back Porch Output

horizontal rate video signals. The vertical output is

produced on the rising edge of the first serration in

• Horizontal Scan Rates to 150 kHz

the vertical sync period. A default vertical output is

• Edge Triggered Vertical Output

produced after a time delay if the rising edge

• Default Triggered Vertical Output for Non-

mentioned above does not occur within the externally

standard Video Signal (Video Games-Home

set delay period, such as might be the case for a

Computers)

non-standard video signal.

(1) PAL in this datasheet refers to European broadcast TV

standard “Phase Alternating Line”, and not to Programmable

Array Logic.

Connection Diagram

Figure 1. LM1881N

See Package Number D0008A or P0008E

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM1881

SNLS384F –FEBRUARY 1995–REVISED MARCH 2013

www.ti.com

Absolute Maximum Ratings

(1)(2)

Supply Voltage 13.2V

Input Voltage 3 V

P-P

= 5V)

6 V

P-P

≥ 8V)

Output Sink Currents; Pins, 1, 3, 5 5 mA

Output Sink Current; Pin 7 2 mA

Package Dissipation

(3)

1100 mW

Storage Temperature Range −65°C to +150°C

ESD Susceptibility

(4)

2 kV

ESD Susceptibility

(5)

200 V

Soldering Information PDIP Package (10 sec.) 260°C

SOIC Package Vapor Phase (60 sec.) 215°C

Infrared (15 sec.) 220°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(3) For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a

package thermal resistance of 110°C/W, junction to ambient.

(4) ESD susceptibility test uses the “human body model, 100 pF discharged through a 1.5 kΩ resistor”.

(5) Machine Model, 220 pF – 240 pF discharged through all pins.

Electrical Characteristics LM1881

= 5V; R

SET

= 680 kΩ; T

= 0°C to +70°C by correlation with 100% electrical testing at T

=25°C

Parameter Conditions Min Typ

(1)

Max Units

Supply Current Outputs at V

= 5V 5.2 10

Logic 1 V

= 12V 5.5 12

DC Input Voltage Pin 2 1.3 1.5 1.8 V

Input Threshold Voltage

(2)

55 70 85 mV

Input Discharge Current Pin 2; V

= 2V 6 11 16 µA

Input Clamp Charge Current Pin 2; V

= 1V 0.2 0.8 mA

SET

Pin Reference Voltage Pin 6;

(3)

1.10 1.22 1.35 V

Composite Sync. & Vertical I

OUT

= 40 µA; V

= 5V 4.0 4.5

Outputs Logic 1 V

= 12V 11.0

OUT

= 1.6 mA V

= 5V 2.4 3.6

Logic 1 V

= 12V 10.0

Burst Gate & Odd/Even Outputs I

OUT

= 40 µA; V

= 5V 4.0 4.5

Logic 1 V

= 12V 11.0

Composite Sync. Output I

OUT

= −1.6 mA; Logic 0; Pin 1 0.2 0.8 V

Vertical Sync. Output I

OUT

= −1.6 mA; Logic 0; Pin 3 0.2 0.8 V

Burst Gate Output I

OUT

= −1.6 mA; Logic 0; Pin 5 0.2 0.8 V

Odd/Even Output I

OUT

= −1.6 mA; Logic 0; Pin 7 0.2 0.8 V

Vertical Sync Width 190 230 300 µs

Burst Gate Width 2.7 kΩ from Pin 5 to V

2.5 4 4.7 µs

Vertical Default Time

(4)

32 65 90 µs

(1) Typicals are at T

= 25°C and represent the most likely parametric norm.

(2) Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.

(3) Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5 and 7) to the R

SET

pin (Pin

6).

(4) Delay time between the start of vertical sync (at input) and the vertical output pulse.

Product Folder Links: LM1881

-40 -20 0 20 40 60 80 100

TEMPERATURE (°C)

100

200

300

400

500

VERTICAL PULSE WIDTH (Ps)

LM1881

www.ti.com

SNLS384F –FEBRUARY 1995–REVISED MARCH 2013

Typical Performance Characteristics

SET

Value Selection Vertical Default Sync Delay Time

vs vs

Vertical Serration Pulse Separation R

SET

Figure 2. Figure 3.

Burst/Black Level Gate Time Vertical Pulse Width

vs vs

SET

Figure 4. Figure 5.

Vertical Pulse Width Supply Current

vs vs

Temperature Supply Voltage

Figure 6. Figure 7.

Product Folder Links: LM1881

Part #	LM1881N
Description	IC VIDEO SYNC SEPARATOR 8-DIP
Category	IC
Availability	In Stock
Qty	10

LM1881N

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