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ispm4k_15z

ispMACH

4000V/B/C/Z Family

3.3V/2.5V/1.8V In-System Programmable

SuperFAST

High Density PLDs

July 2003 Data Sheet

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

NEW!

Industry’s Lowest

Power CPLDs!

ispMACH 4000Z

Features

■

High Performance

•f

MAX

= 400MHz maximum operating frequency

•t

= 2.5ns propagation delay

• Up to four global clock pins with programmable

clock polarity control

• Up to 80 PTs per output

■

Ease of Design

• Enhanced macrocells with individual clock,

reset, preset and clock enable controls

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-Fit

and reﬁt

•Fast path, SpeedLocking

Path, and wide-PT

path

• Wide input gating (36 input logic blocks) for fast

counters, state machines and address decoders

■

Zero Power (ispMACH 4000Z) and Low

Power (ispMACH 4000V/B/C)

•Typical static current 10µA (4032Z)

•Typical static current 1.8mA (4000C)

• 1.8V core low dynamic power

■

Broad Device Offering

• Multiple temperature range support

– Commercial: 0 to 90°C junction (T

)

– Industrial: -40 to 105°C junction (T

)

– Automotive: -40 to 130°C junction (T

)

■

Easy System Integration

• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

• Operation with 3.3V (4000V), 2.5V (4000B) or

1.8V (4000C/Z) supplies

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI

interfaces

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Programmable output slew rate

• 3.3V PCI compatible

• IEEE 1149.1 boundary scan testable

• 3.3V/2.5V/1.8V In-System Programmable

(ISP™) using IEEE 1532 compliant interface

• I/O pins with fast setup path

Table 1. ispMACH 4000V/B/C Family Selection Guide

Note: ispMACH 4032Z information is preliminary. ispMACH 4064Z/4128Z information is advance.

ispMACH

4032V/B/C

ispMACH

4064V/B/C

ispMACH

4128V/B/C

ispMACH

4256V/B/C

ispMACH

4384V/B/C

ispMACH

4512V/B/C

Macrocells 32 64 128 256 384 512

User I/O Options 30/32 30/32/64 64/92/96 64/96/128/160 128/192 128/208

(ns) 2.5 2.5 2.7 3.0 3.5 3.5

(ns) 1.8 1.8 1.8 2.0 2.0 2.0

(ns) 2.2 2.2 2.7 2.7 2.7 2.7

MAX

(MHz) 400 400 333 322 322 322

Supply Voltages (V) 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V

Pins/Package 44 TQFP

48 TQFP

44 TQFP

48 TQFP

100 TQFP 100 TQFP

128 TQFP

144 TQFP

100 TQFP

144 TQFP

176 TQFP

256 fpBGA

176 TQFP

256 fpBGA

176 TQFP

256 fpBGA

1. 3.3V (4000V) only.

2. 128-I/O and 160-I/O conﬁgurations.

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Table 2. ispMACH 4000Z Family Selection Guide

ispMACH 4000 Introduction

The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend

of Lattice’s two most popular architectures: the ispLSI

2000 and ispMACH 4A. Retaining the best of both families,

the ispMACH 4000 architecture focuses on signiﬁcant innovations to combine the highest performance with low

power in a ﬂexible CPLD family.

The ispMACH 4000 combines high speed and low power with the ﬂexibility needed for ease of design. With its

robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-

ity, routing, pin-out retention and density migration.

The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-

binations in Thin Quad Flat Pack (TQFP) and Fine Pitch BGA (fpBGA) packages ranging from 44 to 256 pins/balls.

Table 1 shows the macrocell, package and I/O options, along with other key parameters.

The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)

and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely

driven up to 5.5V when an I/O bank is conﬁgured for 3.3V operation, making this family 5V tolerant. The ispMACH

4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up

resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/

2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary

scan testing capability also allows product testing on automated test equipment.

Overview

The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected

by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which

contain multiple I/O cells. This architecture is shown in Figure 1.

ispMACH 4032ZC

ispMACH 4064ZC

ispMACH 4128ZC

ispMACH 4256ZC

Macrocells 32 64 128 256

User I/O Options 32 32/64 64/96 64/96/128

(ns) 3.5 4.0 4.5 5.0

(ns) 2.2 2.8 2.9 3.0

(ns) 3.0 3.3 3.9 3.9

MAX

(MHz) 267 250 220 200

Supply Voltage (V) 1.8 1.8 1.8 1.8

Standby Icc (µA) 20 25 30 40

Pins/Package 48 TQFP

56 csBGA

48 TQFP

56 csBGA

100 TQFP

132 csBGA

100 TQFP

132csBGA

100 TQFP

132 csBGA

176 TQFP

1. Preliminary information.

2. Advance information.

Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet

Figure 1. Functional Block Diagram

The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can

support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-

patible with the power supply provided to the bank. Support for a variety of standards helps designers implement

designs in mixed voltage environments. In addition, 5V tolerant inputs are speciﬁed within an I/O bank that is con-

nected to V

CCO

of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.

ispMACH 4000 Architecture

There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has

36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be

connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still

must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and

predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-

ated I/O cells in the I/O block.

Generic Logic Block

The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock

generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-

pled from macrocells through the ORP. Figure 2 illustrates the GLB.

I/O

Block

ORP ORP

GOE0

GOE1

GND

TCK

TMS

TDI

TDO

Generic

Logic

Block

Generic

Logic

Block

I/O

Block

ORP ORP

Generic

Logic

Block

Generic

Logic

Block

I/O

Block

I/O Bank 0

I/O Bank 1

I/O

Block

CLK0/I

CLK1/I

CLK2/I

CLK3/I

Global Routing Pool

CCO0

GND

CCO1

GND

16 16

Part #	LC4512V-75F256I
Description	CPLD-EPROM 3.5ns 322 MHz 3.3VSMD/SMT FPBGA-484-100
Category	IC
Availability	In Stock
Qty	47

Qty	Price
1 - 1	$249.27089
2 - 2	$198.28366
3 - 5	$186.95316
6 - 11	$173.73425
12 +	$154.85010

LC4512V-75F256I

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