4 1996 ISP Encyclopedia

Specifications ispLSI and pLSI 1016E

Switching Test Conditions

Figure 2. Test Load

DC Electrical Characteristics

Over Recommended Operating Conditions

Input Pulse Levels

Table 2-0003/1016E

Input Rise and Fall Time

10% to 90%

Input Timing Reference Levels

Ouput Timing Reference Levels

Output Load

GND to 3.0V

1.5V

See figure 2

3-state levels are measured 0.5V from

steady-state active level.

-125

-100, -80

≤ 2 ns

≤ 3 ns

Output Load Conditions (see figure 2)

TEST CONDITION R1 R2 CL

A 470Ω 390Ω 35pF

∞ 390Ω 35pF

470Ω 390Ω 35pF

Active High

Active Low

470Ω 390Ω 5pF

∞ 390Ω 5pF

Active Low to Z

at V +0.5V

Active High to Z

at V -0.5V

Table 2-0004/1016E

+ 5V

Device

Output

Test

Point

includes Test Fixture and Probe Capacitance.

0213a

SYMBOL

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems

by tester ground degradation. Guaranteed but not 100% tested.

2. Measured using four 16-bit counters.

3. Typical values are at V = 5V and T = 25°C.

4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book to estimate maximum

I .

Table 2-0007/1016E

IL-isp

PARAMETER

IL-PU

2, 4

Output Low Voltage

Output High Voltage

Input or I/O High Leakage Current

Input or I/O Low Leakage Current

ispEN Input Low Leakage Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

I = 8 mA

I = -4 mA

3.5V ≤ V ≤ V

0V ≤ V ≤ V (Max.)

0V ≤ V ≤ V

V = 5V, V = 0.5V

V = 0.5V, V = 3.0V

f = 1 MHz

IN IL

IN CC

IN IL

CC OUT

CLOCK

CONDITION MIN. TYP. MAX. UNITS

–

2.4

–

0.4

–

-10

-150

-200

–

µA

CC A

OUT

Commercial

Industrial

5 1996 ISP Encyclopedia

Specifications ispLSI and pLSI 1016E

External Timing Parameters

Over Recommended Operating Conditions

pd1

UNITS

-125

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions Section.

Table 2-0030-16/125,100, 80

tsu2 + tco1

( )

-100

MIN.MAX. MAX.

DESCRIPTION#

PARAMETER

A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns

pd2

A 2 Data Prop. Delay, Worst Case Path – – ns

max

A 3 Clk. Frequency with Int. Feedback 125 – 100 – MHz

max (Ext.)

– 4 Clk. Frequency with Ext. Feedback – – MHz

max (Tog.)

– 5 Clk. Frequency, Max. Toggle – – MHz

su1

– 6 GLB Reg. Setup Time before Clk., 4 PT Bypass – – ns

co1

A 7 GLB Reg. Clk. to Output Delay, ORP Bypass – – ns

– 8 GLB Reg. Hold Time after Clk., 4 PT Bypass 0.0 – ns

su2

– 9 GLB Reg. Setup Time before Clk. 5.5 – ns

co2

– 10 GLB Reg. Clk. to Output Delay – – ns

– 11 GLB Reg. Hold Time after Clk. 0.0 – ns

A 12 Ext. Reset Pin to Output Delay – – ns

rw1

– 13 Ext. Reset Pulse Duration 5.0 – ns

ptoeen

B 14 Input to Output Enable – – ns

ptoedis

C 15 Input to Output Disable – – ns

wh – 18 Ext. Sync. Clk. Pulse Duration, High 3.0 4.0 ns

– 19 Ext. Sync. Clk. Pulse Duration, Low 3.0 4.0 ns

su3

– 20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0 – – ns

– 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3) 0.0 – – ns

100

167

5.0

4.5

–

5.5

–

10.0

–

12.0

–

10.0

125

7.0

0.0

8.0

0.0

6.5

3.5

0.0

13.0

5.0

6.0

13.5

15.0

–

( )

twh + tw1

goeen

B 16 Global OE Output Enable – – ns7.0 9.0

goedis

C 17 Global OE Output Disable – – ns7.0 9.0

-80

MIN. MAX.

–

15.0

18.5

84.0

57.0

100

8.5

8.0

0.0

9.5

0.0

17.0

10.0

20.0

10.5

5.0

0.0

4.5

5.0

–

6 1996 ISP Encyclopedia

Specifications ispLSI and pLSI 1016E

Internal Timing Parameters

iobp

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR Adjacent path can only be used by Lattice hard macros.

Table 2-0036-16/125,100, 80

Inputs

UNITS

-125

MIN.

-100

MIN.MAX. MAX.

DESCRIPTION

PARAMETER

22 I/O Register Bypass

– – 0.4 ns

iolat

23 I/O Latch Delay

– – 2.4 ns

grp1

29 GRP Delay, 1 GLB Load

– – 1.9 ns

GLB

1ptxor

36 1 Product Term/XOR Path Delay

––

6.1

20ptxor

37 20 Product Term/XOR Path Delay

––

6.1

xoradj

38 XOR Adjacent Path Delay

––

6.6

gbp

39 GLB Register Bypass Delay

––

1.6

gsu

40 GLB Register Setup Time before Clock

– 0.2 – ns

41 GLB Register Hold Time after Clock

– 2.5 – ns

gco

42 GLB Register Clock to Output Delay

– – 1.9 ns

gro

43 GLB Register Reset to Output Delay

– – 6.3 ns

ptre

44 GLB Product Term Reset to Register Delay

– – 5.1 ns

ptoe

45 GLB Product Term Output Enable to I/O Cell Delay

– – 7.1 ns

ptck

46 GLB Product Term Clock Delay

4.8 5.3 ns

ORP

0.3

1.8

GRP

1.8

4ptbpc

34 4 Product Term Bypass Path Delay (Combinatorial)

––

5.7

4.4

1.0

3.9

4ptbpr

35 4 Product Term Bypass Path Delay (Registered)

––

5.6

3.9

0.2

1.5

1.8

4.4

3.5

5.5

3.2 3.5

orp

47 ORP Delay

– – 1.0 ns

orpbp

48 ORP Bypass Delay

– – 0.0 ns

1.0

0.0

iosu

24 I/O Register Setup Time before Clock

3.0 3.5 – ns–

ioh

25 I/O Register Hold Time after Clock

-0.3 -0.4 – ns–

ioco

26 I/O Register Clock to Out Delay

– – 5.0 ns4.0

ior

27 I/O Register Reset to Out Delay

– – 5.0 ns4.0

din

28 Dedicated Input Delay

– – 2.6 ns2.2

-80

MIN. MAX.

–

0.6

3.6

4.5

-0.6

7.5

3.9

2.9

7.1

8.2

8.3

1.9

8.1

7.3

-0.6

4.3

2.9

7.0

7.2

9.7

6.8 7.5

1.5

0.0

grp16

32 GRP Delay, 16 GLB Loads

––

3.1

grp4

30 GRP Delay, 4 GLB Loads

––

2.2

2.4

1.9

grp8

31 GRP Delay, 8 GLB Loads

––

2.5

2.1

–

4.7

3.3

3.8

Part #	ISPLSI1016E-80LJ
Description	Complex Programmable LogicDevices USE ispMACH 4000V
Category	IC
Availability	Out of Stock
Qty	0

ISPLSI1016E-80LJ

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