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CD4541BCM

Part # CD4541BCM
Description IC OSC PROG TIMER 100KHZ 14SOIC
Category IC
Availability In Stock
Qty 94
Qty Price
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20 - 39 $2.21151
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79 + $1.72708
Manufacturer Available Qty
Fairchild Semiconductor
Date Code: 1043
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

October 1987
Revised March 1999
CD4541BC Programmable Timer
© 1999 Fairchild Semiconductor Corporation DS006001.prf www.fairchildsemi.com
CD4541BC
Programmable Timer
General Description
The CD4541BC Programmable Timer is designed with a
16-stage binary counter, an integrated oscillator for use
with an external capacitor and two resistors, output control
logic, and a special power-on reset circuit. The special fea-
tures of the power-on reset circuit are first, no additional
static power consumption and second, the part functions
across the full voltage range (3V–15V) whether power-on
reset is enabled or disabled.
Timing and the counter are initialized by turning on power,
if the power-on reset is enabled. When the power is
already on, an external reset pulse will also initialize the
timing and counter. After either reset is accomplished, the
oscillator frequency is determined by the external RC net-
work. The 16-stage counter divides the oscillator frequency
by any of 4 digitally controlled division ratios.
Features
Available division ratios 2
8
, 2
10
, 2
13
, or 2
16
Increments on positive edge clock transitions
Built-in low power RC oscillator (±2% accuracy over
temperature range and ±10% supply and ±3% over pro-
cessing @ < 10 kHz)
Oscillator frequency range DC to 100 kHz
Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
Automatic reset initializes all counters when power turns
on
External master reset totally independent of automatic
reset operation
Operates at 2
n
frequency divider or single transition
timer
Q/Q
select provides output logic level flexibility
Reset (auto or master) disables oscillator during reset-
ting to provide no active power dissipation
Clock conditioning circuit permits operation with very
slow clock rise and fall times
Wide supply voltage range—3.0V to 15V
High noise immunity—0.45 V
DD
(typ.)
5V–10V–15V parameter ratings
Symmetrical output characteristics
Maximum input leakage 1 µA at 15V over full tempera-
ture range
High output drive (pin 8) min. one TTL load
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
N.C.—Not connected
Top View
Order Number Package Number Package Description
CD4541BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4541BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
www.fairchildsemi.com 2
CD4541BC
Truth Table Division Ratio Table
Operating Characteristics
With Auto Reset pin set to a “0” the counter circuit is initial-
ized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to
a “1”. Both types of reset will result in synchronously reset-
ting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external
RC network, i.e.:
and R
S
2 R
tc
where R
S
10 k
The time select inputs (A and B) provide a two-bit address
to output any one of four counter stages (2
8
, 2
10
, 2
13
, and
2
16
). The 2
n
counts as shown in the Division Ratio Table
represent the Q output of the Nth stage of the counter.
When A is “1”, 2
16
is selected for both states of B.
However, when B is “0”, normal counting is interrupted and
the 9th counter stage receives its clock directly from the
oscillator (i.e., effectively outputting 2
8
).
The Q/Q
select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q
select pin is set to a “0” the Q output is a “0”. Corre-
spondingly, when Q/Q
select pin is set to a “1” the Q output
is a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip-flop
resets (see Logic Diagram), counting commences and after
2
n1
counts the RS flip-flop sets which causes the output to
change state. Hence, after another 2
n1
counts the output
will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to
reset the single cycle operation.
Typical RC Oscillator
Characteristics
Solid Line = R
TC
= 56 k, R
S
= 1 k and C = 1000 pF
f = 10.2 kHz @ V
DD
= 10V and T
A
= 25°
Dashed Line = R
TC
= 56 k, R
S
= 120 k and C = 1000 pF
f = 7.75 kHz @ V
DD
= 10V and T
A
= 25°
RC Oscillator Frequency as a
Function of R
TC
and C
Line A: f as a function of C and (R
TC
= 56 k; R
S
= 120k
Line B: f as a function of R
TC
and (C = 100 pF; R
S
= 2 R
TC
Pin State
01
5 Auto Reset Operating Auto Reset Disabled
6 Timer Operational Master Reset On
9 Output Initially Low Output Initially High
after Reset after Reset
10 Single Cycle Mode Recycle Mode
Number of Count
A B Counter Stages
2
n
n
0 0 13 8192
0 1 10 1024
10 8 256
1 1 16 65536
3 www.fairchildsemi.com
CD4541BC
Oscillator Circuit Using RC Configuration
Logic Diagram
V
DD
= Pin 14
V
SS
= Pin 7
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