Dual Output Digital Multi-Phase Controller
August 9, 2012 | FINAL | Product Brief | V2.04
FEATURES
Dual output 6+2 phase PWM Controller
Easiest layout and fewest pins in the industry
Fully supports AMD® SVI1 & SVI2 with dual OCP
and Intel® VR12 & VR12.5
Overclocking & Gaming Mode
Switching frequency from 200kHz to 2MHz
per phase
IR Efficiency Shaping Features including
Dynamic Phase Control and Automatic Power
State Switching
Programmable 1-phase or 2-phase operation for
Light Loads and Active Diode Emulation for Very
Light Loads
IR Adaptive Transient Algorithm (ATA) on both
loops minimizes output bulk capacitors and
system cost
Auto-Phase Detection with auto-compensation
Per-Loop Fault Protection: OVP, UVP, OCP,
OTP, CFP
I2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
Multiple Time Programming (MTP) with
integrated charge pump for easy custom
configuration
Compatible with IR ATL and 3.3V tri-state Drivers
+3.3V supply voltage; -20°C to 85°C ambient
operation
Pb-Free, RoHS, 7x7mm, 56-pin, 0.4mm pitch QFN
BASIC APPLICATION
PWM1
12V
VOUT1
ISEN1
IRTN1
3.3V
SVD
ENABLE
ENABLE
SVC
IR3567A
VR_RDY_L1
SVT
VR_HOT#
PWM6
ISEN6
IRTN6
PWM1_L2
ISEN1_L2
IRTN1_L2
Power
Stage 7
.
.
.
VCC
PWM2_L2
ISEN2_L2
IRTN2_L2
Power
Stage 6
Power
Stage 1
VOUT2
VR_RDY_L2
VR_RDY_L1
VR_RDY_L2
VR_HOT#
SVD
SVC
SVT
Power
Stage 8
Figure 1: IR3567A Basic Application Circuit
DESCRIPTION
The IR3567A is a dual-loop digital multi-phase buck controller
designed for CPU voltage regulation and is fully compliant with
AMD® SVI1 & SVI2 and Intel
©
VR12 & VR12.5 specifications.
The IR3567A includes IR’s Efficiency Shaping Technology
to deliver exceptional efficiency at minimum cost across the
entire load range. IR Variable Gate Drive optimizes the
MOSFET gate drive voltage based on real-time load current.
IR’s Dynamic Phase Control adds/drops active phases based
upon load current and can be configured to enter 1-phase
operation and diode emulation mode automatically or by
command.
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors and Multiple Time Programmable
(MTP) storage saves pins and enables a small package size.
Device configuration and fault parameters are easily defined
using the IR Digital Power Design Center (DPDC) GUI and
stored in on-chip MTP.
The IR3567A provides extensive OVP, UVP, OCP and OTP fault
protection and includes thermistor based temperature sensing
with VRHOT signal.
The IR3567A includes numerous features like register
diagnostics for fast design cycles and platform differentiation,
simplifying VRD design and enabling fastest time-to-market
(TTM) with “set-and-forget” methodology.
APPLICATIONS
AMD® SVI1 & SVI2, Intel® VR12 & VR12.5 based systems
Desktop & Notebook CPU VRs
High Performance Graphics Processors
PIN DIAGRAM
SM_ALERT#
PWM5
ISEN2_L2
EN
VRTN
RCSM
ISEN5
ISEN4
ISEN3
PWM6
VSEN
SM_DIO
PWM4
PWRGD/
VRDY1
IRTN3
IRTN4
IRTN2_L2
IRTN5
RCSP
TSEN1
VRHOT_ICRIT#
PWM3
VINSEN
ADDR_PROT
V18 A
RRES
VCC
ISEN2
ISEN1
IRTN1
IRTN2
PWM2
PWM1
NC
RCSM_L2
RCSP_L2
SM_CLK
CFP
NC
PWROK/EN_L2/
INMODE
VRDY2
PWM2_L2
VRTN_L2
VSEN_L2
57 GND
IR3567A
56 Pin 7 x 7 QFN
Top View
55 5153 4854 5052 474956 46 45 4344
1
2
7
8
5
6
3
4
10
9
12
11
14
13
16 2018 2317 2119 242215 25 26 2827
42
41
36
35
38
37
40
39
33
34
31
32
29
30
ISEN 6
NC
VARGATE
PWM1_L2
ISEN1_L2
I RTN1_L2
IRTN6
VDDIO/
SV_ADDR
SVT/
SV_ALERT
SV_DIO/
VIDSEL0
SV_CLK/
VIDSEL1
TSNE2/
VAUXSEN
Figure 2: IR3567A Package Top View
