Generic 18CV8P-7

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1 04-02-004H
International
CMOS
Technology
®
Commercial
/
Industrial
The PEEL18CV8 architecture allows it to replace over 20
standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro-
vides additional architecture features so more logic can be
put into every design. ICT’s JEDEC file translator instantly
converts to the PEEL18CV8 existing 20-pin PLDs without
the need to rework the existing design. Development and
programming support for the PEEL18CV8 is provided by
popular third-party programmers and development software.
ICT also offers free PLACE development software and a
low-cost development system (PDS-3).
Figure 2 Block Diagram
General Description
The PEEL18CV8 is a Programmable Electrically Erasable
Logic (PEEL) device providing an attractive alternative to
ordinary PLDs. The PEEL18CV8 offers the performance,
flexibility, ease of design and production practicality needed
by logic designers today.
The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC
and TSSOP packages with speeds ranging from 5ns to
25ns with power consumption as low as 37mA. EE-Repro-
grammability provides the convenience of instant repro-
gramming for development and reusable production
inventory minimizing the impact of programming changes
or errors. EE-Reprogrammability also improves factory
testability, thus assuring the highest quality possible.
Figure 1 Pin Configuration
PLCC
DIP
SOIC
1
2
3
4
5
6
7
8
9
10
I/CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
20
19
18
17
16
15
14
13
12
11
TSSOP
PEEL™ 18CV8 -5/-7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
Multiple Speed Power, Temperature Options
- V
CC
= 5 Volts ±10%
- Speeds ranging from 5ns to 25 ns
- Power as low as 37mA at 25MHz
- Commercial and industrial versions available
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
programmer
- PLD-to-PEEL JEDEC file translator
Architectural Flexibility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
-- 20 Pin DIP/SOIC/TSSOP and PLCC
Application Versatility
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary
PLDs
2 04-02-004H
International
CMOS
Technology
®
PEEL
TM
18CV8
Figure 3 PEEL18CV8 Logic Array Diagram
3 04-02-004H
International
CMOS
Technology
®
PEEL
TM
18CV8
Function Description
The PEEL18CV8 implements logic functions as sum-of-
products expressions in a programmable-AND/fixed-OR
logic array. User-defined functions are created by program-
ming the connections of input signals into the array. User-
configurable output structures in the form of I/O macrocells
further increase logic flexibility.
Architecture Overview
The PEEL18CV8 architecture is illustrated in the block dia-
gram of Figure 2. Ten dedicated inputs and 8 I/Os provide
up to 18 inputs and 8 outputs for creation of logic functions.
At the core of the device is a programmable electrically-
erasable AND array which drives a fixed OR array. With
this structure, the PEEL18CV8 can implement up to 8 sum-
of-products logic expressions.
Associated with each of the 8 OR functions is an I/O mac-
rocell which can be independently programmed to one of
12 different configurations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic
functions of active-high or active-low polarity, while provid-
ing three different feedback paths into the AND array.
AND/OR LOGIC ARRAY
The programmable AND array of the PEEL18CV8 (shown
in Figure 3) is formed by input lines intersecting product
terms. The input lines and product terms are used as fol-
lows:
36 Input Lines:
- 20 input lines carry the true and complement of the
signals applied to the 10 input pins
- 16 additional lines carry the true and complement val-
ues of feedback or input signals from the 8 I/Os
74 product terms:
- 64 product terms (arranged in groups of 8) are used
to form sum of product functions
- 8 output enable terms (one for each I/O)
- 1 global synchronous preset term
- 1 global asynchronous clear term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 36-input AND gate. A product term
that is connected to both the true and complement of an
input signal will always be FALSE and thus will not affect
the OR function that it drives. When all the connections on
a product term are opened, a “don’t care” state exists and
that term will always be TRUE.
When programming the PEEL18CV8, the device program-
mer first performs a bulk erase to remove the previous pat-
tern. The erase cycle opens every logical connection in the
array. The device is configured to perform the user-defined
function by programming selected connections in the AND
array. (Note that PEEL device programmers automatically
program all of the connections on unused product terms so
that they will have no effect on the output function).
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides
complete control over the architecture of each output. The
ability to configure each output independently permits
users to tailor the configuration of the PEEL18CV8 to the
precise requirements of their designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 4, consists of a D-
type flip-flop and two signal-select multiplexers. The config-
uration of each macrocell is determined by the four
EEPROM bits controlling these multiplexers. These bits
determine output polarity, output type (registered or non-
registered) and input-feedback path (bidirectional I/O, com-
binatorial feedback). Refer to Table 1 for details.
Equivalent circuits for the twelve macrocell configurations
are illustrated in Figure 5. In addition to emulating the four
PAL-type output structures (configurations 3,4,9, and 10),
the macrocell provides eight additional configurations.
When creating a PEEL device design, the desired macro-
cell configuration generally is specified explicitly in the
design file. When the design is assembled or compiled, the
macrocell configuration bits are defined in the last lines of
the JEDEC programming file.
Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type flip-
flop (registered function). The D-type flip-flop latches data
on the rising edge of the clock and is controlled by the glo-
bal preset and clear terms. When the synchronous preset
term is satisfied, the Q output of the register will be set
HIGH at the next rising edge of the clock input. Satisfying
the asynchronous clear will set Q LOW, regardless of the
clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is switched into the high-impedance state.
Under the control of the output enable term, the I/O pin can
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