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IS82C54-10

Part # IS82C54-10
Description PERIPH PRG-CNTR 5V 10MHZ 28PLCC IND
Category IC
Availability Out of Stock
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1 + $2.32553



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

4-13
)
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C54, C82C54-10, -12 . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
I82C54, I82C54-10, -12 . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
M82C54, M82C54-10, -12 . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Thermal Resistance (Typical) θ
JA
(
o
C/W) θ
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . . 55 12
CLCC Package . . . . . . . . . . . . . . . . . . 65 14
PDIP Package . . . . . . . . . . . . . . . . . . . 60 N/A
PLCC Package . . . . . . . . . . . . . . . . . . 65 N/A
SOIC Package. . . . . . . . . . . . . . . . . . . 75 N/A
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature Ceramic Package . . . . . . . +175
o
C
Maximum Junction Temperature Plastic Package. . . . . . . . . +150
o
C
Maximum Lead Temperature Package (Soldering 10s) . . . . +300
o
C
(PLCC and SOIC - Lean Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2250 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications V
CC
= +5.0V ± 10%, T
A
= 0
o
C to +70
o
C (C82C54, C82C54-10, C82C54-12)
T
A
= -40
o
C to +85
o
C (I82C54, I82C54-10, I82C54-12)
T
A
= -55
o
C to +125
o
C (M82C54, M82C54-10, M82C54-12
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
VIH Logical One Input Voltage 2.0 - V C82C54, I82C54
2.2 - V M82C54
VIL Logical Zero Input Voltage - 0.8 V
VOH Output HIGH Voltage 3.0 - V IOH = -2.5mA
V
CC
-0.4 - V IOH = -100µA
VOL Output LOW Voltage - 0.4 V IOL = +2.5mA
II Input Leakage Current -1 +1 µA VIN = GND or V
CC
DIP Pins 9,11,14-16,18-23
IO Output Leakage Current -10 +10 µA VOUT = GND or V
CC
DIP Pins 1-8
ICCSB Standby Power Supply Current - 10 µAV
CC
= 5.5V, VIN = GND or V
CC
,
Outputs Open, Counters
Programmed
ICCOP Operating Power Supply Current - 10 mA V
CC
= 5.5V,
CLK0 = CLK1 = CLK2 = 8MHz,
VIN = GND or V
CC
,
Outputs Open
Capacitance T
A
= +25
o
C; All Measurements Referenced to Device GND, Note 1
SYMBOL PARAMETER TYP UNITS TEST CONDITIONS
CIN Input Capacitance 20 pF FREQ = 1MHz
COUT Output Capacitance 20 pF FREQ = 1MHz
CI/O I/O Capacitance 20 pF FREQ = 1MHz
NOTE:
1. Not tested, but characterized at initial design and at major process/design changes.
82C54
4-14
AC Electrical Specifications V
CC
= +5.0V ± 10%, T
A
= 0
o
C to +70
o
C (C82C54, C82C54-10, C82C54-12)
T
A
= -40
o
C to +85
o
C (I82C54, I82C54-10, I82C54-12)
T
A
= -55
o
C to +125
o
C (M82C54, M82C54-10, M82C54-12)
SYMBOL PARAMETER
82C54 82C54-10 82C54-12
UNITS
TEST
CONDITIONSMIN MAX MIN MAX MIN MAX
READ CYCLE
(1) TAR Address Stable Before RD 30 - 25 - 25 - ns 1
(2) TSR CS Stable Before RD 0-0-0-ns 1
(3) TRA Address Hold Time After RD0-0-0-ns 1
(4) TRR RD Pulse Width 150 - 95 - 95 - ns 1
(5) TRD Data Delay from RD - 120 - 85 - 85 ns 1
(6) TAD Data Delay from Address - 210 - 185 - 185 ns 1
(7) TDF RD to Data Floating 5 85 5 65 5 65 ns 2, Note 1
(8) TRV Command Recovery Time 200 - 165 - 165 - ns
WRITE CYCLE
(9) TAW Address Stable Before WR 0-0-0-ns
(10) TSW CS Stable Before WR 0-0-0-ns
(11) TWA Address Hold Time After WR0-0-0-ns
(12) TWW WR Pulse Width 95 - 95 - 95 - ns
(13) TDW Data Setup Time Before WR 140 - 95 - 95 - ns
(14) TWD Data Hold Time After WR 25 - 0 - 0 - ns
(15) TRV Command Recovery Time 200 - 165 - 165 - ns
CLOCK AND GATE
(16) TCLK Clock Period 125 DC 100 DC 80 DC ns 1
(17) TPWH High Pulse Width 60 - 30 - 30 - ns 1
(18) TPWL Low Pulse Width 60 - 40 - 30 - ns 1
(19) TR Clock Rise Time - 25 - 25 - 25 ns
(20) TF Clock Fall Time - 25 - 25 - 25 ns
(21) TGW Gate Width High 50 - 50 - 50 - ns 1
(22) TGL Gate Width Low 50 - 50 - 50 - ns 1
(23) TGS Gate Setup Time to CLK 50 - 40 - 40 - ns 1
(24) TGH Gate Hold Time After CLK 50 - 50 - 50 - ns 1
(25) TOD Output Delay from CLK - 150 - 100 - 100 ns 1
(26) TODG Output Delay from Gate - 120 - 100 - 100 ns 1
(27) TWO OUT Delay from Mode Write - 260 - 240 - 240 ns 1
(28) TWC CLK Delay for Loading 0 55 0 55 0 55 ns 1
(29) TWG Gate Delay for Sampling -5 40 -5 40 -5 40 ns 1
(30) TCL CLK Setup for Count Latch -40 40 -40 40 -40 40 ns 1
NOTE:
1. Not tested, but characterized at initial design and at major process/design changes.
82C54
4-15
Timing Waveforms
FIGURE 17. WRITE
FIGURE 18. READ
FIGURE 19. RECOVERY
FIGURE 20. CLOCK AND GATE
A0 - A1
CS
DATA BUS
WR
(12)
tWW
(13)
tDW
(10)
tSW
(9)
tAW
VALID
tWD (14)
tWA (11)
VALID
A0 - A1
CS
RD
DATA BUS
(2)
tSR
(6)
tAD
(5)
tRD
(4)
tRR
(7)
tDF
tRA (3)
tAR (1)
(8) (15)
tRV
RD, WR
WR
CLK
GATE
OUT
MODE
COUNT
(SEE NOTE)
(17)
tPWH
(18)
tPWL
(16)
tCLK
tGS
(21)
tGW
(27)
tWO
tGS
(23)
tGH
(24)
tGL
tODG (26)
tF (20)
tOD (25)
tGH (24)
NOTE: LAST BYTE OF COUNT BEING WRITTEN
(19)
tR
(22)
(23)
tCL (30)
tWC (28)
82C54
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