4-7

1.Read least signiﬁcant byte.

2.Write new least signiﬁcant byte.

3.Read most signiﬁcant byte.

4.Write new most signiﬁcant byte.

If a counter is programmed to read or write two-byte counts,

the following precaution applies: A program MUST NOT

transfer control between reading the ﬁrst and second byte to

another routine which also reads from that same Counter.

Otherwise, an incorrect count will be read.

Read-Back Command

The read-back command allows the user to check the count

value, programmed Mode, and current state of the OUT pin

and Null Count ﬂag of the selected counter(s).

The command is written into the Control Word Register and

has the format shown in Figure 5. The command applies to

the counters selected by setting their corresponding bits D3,

D2, D1 = 1.

The read-back command may be used to latch multiple

counter output latches (OL) by setting the COUNT bit D5 = 0

and selecting the desired counter(s). This signal command

is functionally equivalent to several counter latch commands,

one for each counter latched. Each counter’s latched count

is held until it is read (or the counter is reprogrammed). That

counter is automatically unlatched when read, but other

counters remain latched until they are read. If multiple count

read-back commands are issued to the same counter with-

out reading the count, all but the ﬁrst are ignored; i.e., the

count which will be read is the count at the time the ﬁrst

read-back command was issued.

The read-back command may also be used to latch status

information of selected counter(s) by setting STATUS bit D4

= 0. Status must be latched to be read; status of a counter is

accessed by a read from that counter.

The counter status format is shown in Figure 6. Bits D5

through D0 contain the counter’s programmed Mode exactly

as written in the last Mode Control Word. OUTPUT bit D7

contains the current state of the OUT pin. This allows the

user to monitor the counter’s output via software, possibly

eliminating some hardware from a system.

NULL COUNT bit D6 indicates when the last count written to

the counter register (CR) has been loaded into the counting

element (CE). The exact time this happens depends on the

Mode of the counter and is described in the Mode Deﬁnitions,

but until the counter is loaded into the counting element (CE),

it can’t be read from the counter. If the count is latched or read

before this time, the count value will not reﬂect the new count

just written. The operation of Null Count is shown below.

THIS ACTION: CAUSES:

A. Write to the control word register:(1) . . . . . . . . . . Null Count = 1

B. Write to the count register (CR):(2) . . . . . . . . . . . Null Count = 1

C. New count is loaded into CE (CR - CE). . . . . . . . Null Count = 0

(1) Only the counter speciﬁed by the control word will have its null

count set to 1. Null count bits of other counters are unaffected.

(2) If the counter is programmed for two-byte counts (least signiﬁ-

cant byte then most signiﬁcant byte) null count goes to 1 when

the second byte is written.

If multiple status latch operations of the counter(s) are per-

formed without reading the status, all but the ﬁrst are ignored;

i.e., the status that will be read is the status of the counter at

the time the ﬁrst status read-back command was issued.

FIGURE 7. READ-BACK COMMAND EXAMPLE

A0, A1 = 11; CS = 0; RD = 1; WR = 0

D7 D6 D5 D4 D3 D2 D1 D0

11COUNT STATUS CNT 2 CNT 1 CNT 0 0

D5: 0 = Latch count of selected Counter (s)

D4: 0 = Latch status of selected Counter(s)

D3: 1 = Select Counter 2

D2: 1 = Select Counter 1

D1: 1 = Select Counter 0

D0: Reserved for future expansion; Must be 0

FIGURE 5. READ-BACK COMMAND FORMAT

D7 D6 D5 D4 D3 D2 D1 D0

OUTPUT NULL

COUNT

RW1 RW0 M2 M1 M0 BCD

D7: 1 = Out pin is 1

0 = Out pin is 0

D6: 1 = Null count

0 = Count available for reading

D5 - D0 =Counter programmed mode (See Control Word Formats)

FIGURE 6. STATUS BYTE

COMMANDS

DESCRIPTION RESULTD7 D6 D5 D4 D3 D2 D1 D0

11000010Read-Back Count and Status of Counter 0 Count and Status Latched for Counter 0

11100100Read-Back Status of Counter 1 Status Latched for Counter 1

11101100Read-Back Status of Counters 2, 1 Status Latched for Counter 2,

But Not Counter 1

11011000Read-Back Count of Counter 2 Count Latched for Counter 2

11000100Read-Back Count and Status of Counter 1 Count Latched for Counter 1,

But Not Status

11100010Read-Back Status of Counter 1 Command Ignored, Status Already

Latched for Counter 1

82C54

4-8

Both count and status of the selected counter(s) may be

latched simultaneously by setting both COUNT and STATUS

bits D5, D4 = 0. This is functionally the same as issuing two

separate read-back commands at once, and the above dis-

cussions apply here also. Speciﬁcally, if multiple count

and/or status read-back commands are issued to the same

counter(s) without any intervening reads, all but the ﬁrst are

ignored. This is illustrated in Figure 7.

If both count and status of a counter are latched, the ﬁrst

read operation of that counter will return latched status,

regardless of which was latched ﬁrst. The next one or two

reads (depending on whether the counter is programmed for

one or two type counts) return latched count. Subsequent

reads return unlatched count.

Mode Deﬁnitions

The following are deﬁned for use in describing the operation

of the 82C54.

CLK PULSE:

A rising edge, then a falling edge, in that order, of a

Counter’s CLK input.

TRIGGER:

A rising edge of a Counter’s Gate input.

COUNTER LOADING:

The transfer of a count from the CR to the CE (See “Func-

tional Description”)

Mode 0: Interrupt on Terminal Count

Mode 0 is typically used for event counting. After the Control

Word is written, OUT is initially low, and will remain low until

the Counter reaches zero. OUT then goes high and remains

high until a new count or a new Mode 0 Control Word is writ-

ten to the Counter.

GATE = 1 enables counting; GATE = 0 disables counting.

GATE has no effect on OUT.

After the Control Word and initial count are written to a

Counter, the initial count will be loaded on the next CLK

pulse. This CLK pulse does not decrement the count, so for

an initial count of N, OUT does not go high until N + 1 CLK

pulses after the initial count is written.

If a new count is written to the Counter it will be loaded on

the next CLK pulse and counting will continue from the new

count. If a two-byte count is written, the following happens:

(1)Writing the ﬁrst byte disables counting. Out is set low

immediately (no clock pulse required).

(2)Writing the second byte allows the new count to be

loaded on the next CLK pulse.

This allows the counting sequence to be synchronized by

software. Again OUT does not go high until N + 1 CLK

pulses after the new count of N is written.

If an initial count is written while GATE = 0, it will still be

loaded on the next CLK pulse. When GATE goes high, OUT

will go high N CLK pulses later; no CLK pulse is needed to

load the counter as this has already been done.

FIGURE 9. MODE 0

NOTES: The following conventions apply to all mode timing diagrams.

1. Counters are programmed for binary (not BCD) counting and for

reading/writing least signiﬁcant byte (LSB) only.

2. The counter is always selected (

CS always low).

3. CW stands for “Control Word”; CW = 10 means a control word of

10, Hex is written to the counter.

4. LSB stands for Least significant “byte” of count.

5. Numbers below diagrams are count values. The lower number is

the least significant byte. The upper number is the most signifi-

cant byte. Since the counter is programmed to read/write LSB

only, the most significant byte cannot be read.

6. N stands for an undefined count.

7. Vertical lines show transitions between count values.

CS RD WR A1 A0

01000Write into Counter 0

01001Write into Counter 1

01010Write into Counter 2

01011Write Control Word

00100Read from Counter 0

00101Read from Counter 1

00110Read from Counter 2

00111No-Operation (Three-State)

1XXXXNo-Operation (Three-State)

0 1 1 X X No-Operation (Three-State)

FIGURE 8. READ/WRITE OPERATIONS SUMMARY

CW = 10 LSB = 4

CLK

GATE

OUT

CLK

GATE

OUT

CLK

GATE

OUT

CW = 10 LSB = 3

LSB = 2

NNNN

82C54

4-9

Mode 1: Hardware Retriggerable One-Shot

OUT will be initially high. OUT will go low on the CLK pulse

following a trigger to begin the one-shot pulse, and will remain

low until the Counter reaches zero. OUT will then go high and

remain high until the CLK pulse after the next trigger.

After writing the Control Word and initial count, the Counter is

armed. A trigger results in loading the Counter and setting

OUT low on the next CLK pulse, thus starting the one-shot

pulse N CLK cycles in duration. The one-shot is retriggerable,

hence OUT will remain low for N CLK pulses after any trigger.

The one-shot pulse can be repeated without rewriting the

same count into the counter. GATE has no effect on OUT.

If a new count is written to the Counter during a one-shot

pulse, the current one-shot is not affected unless the

Counter is retriggerable. In that case, the Counter is loaded

with the new count and the one-shot pulse continues until

the new count expires.

FIGURE 10. MODE 1

Mode 2: Rate Generator

This Mode functions like a divide-by-N counter. It is typically

used to generate a Real Time Clock Interrupt. OUT will ini-

tially be high. When the initial count has decremented to 1,

OUT goes low for one CLK pulse. OUT then goes high

again, the Counter reloads the initial count and the process

is repeated. Mode 2 is periodic; the same sequence is

repeated indeﬁnitely. For an initial count of N, the sequence

repeats every N CLK cycles.

GATE = 1 enables counting; GATE = 0 disables counting. If

GATE goes low during an output pulse, OUT is set high

immediately. A trigger reloads the Counter with the initial

count on the next CLK pulse; OUT goes low N CLK pulses

after the trigger. Thus the GATE input can be used to syn-

chronize the Counter.

After writing a Control Word and initial count, the Counter will

be loaded on the next CLK pulse. OUT goes low N CLK

pulses after the initial count is written. This allows the

Counter to be synchronized by software also.

Writing a new count while counting does not affect the current

counting sequence. If a trigger is received after writing a new

count but before the end of the current period, the Counter will

be loaded with the new count on the next CLK pulse and count-

ing will continue from the end of the current counting cycle.

FIGURE 11. MODE 2

CLK

GATE

OUT

CLK

GATE

OUT

CLK

GATE

OUT

NNNN

CW = 12 LSB = 3

CW = 12 LSB = 2

LSB = 4

NNNN

CLK

GATE

OUT

CW = 14 LSB = 3

CLK

GATE

OUT

CW = 14 LSB = 3

CLK

GATE

OUT

CW = 14 LSB = 4 LSB = 5

82C54

Part #	IS82C54-10
Description	PERIPH PRG-CNTR 5V 10MHZ 28PLCC IND
Category	IC
Availability	Out of Stock
Qty	0

IS82C54-10

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Technical Document