4-4

Control Word Register

The Control Word Register (Figure 2) is selected by the

Read/Write Logic when A1, A0 = 11. If the CPU then does a

write operation to the 82C54, the data is stored in the Con-

trol Word Register and is interpreted as a Control Word used

to deﬁne the Counter operation.

The Control Word Register can only be written to; status

information is available with the Read-Back Command.

Counter 0, Counter 1, Counter 2

These three functional blocks are identical in operation, so

only a single Counter will be described. The internal block

diagram of a signal counter is shown in Figure 3. The

counters are fully independent. Each Counter may operate

in a different Mode.

The Control Word Register is shown in the ﬁgure; it is not

part of the Counter itself, but its contents determine how the

Counter operates.

The status register, shown in the ﬁgure, when latched, con-

tains the current contents of the Control Word Register and

status of the output and null count ﬂag. (See detailed expla-

nation of the Read-Back command.)

The actual counter is labeled CE (for Counting Element). It is

a 16-bit presettable synchronous down counter.

OLM and OLL are two 8-bit latches. OL stands for “Output

Latch”; the subscripts M and L for “Most signiﬁcant byte” and

“Least signiﬁcant byte”, respectively. Both are normally referred

to as one unit and called just OL. These latches normally “fol-

low” the CE, but if a suitable Counter Latch Command is sent to

the 82C54, the latches “latch” the present count until read by

the CPU and then return to “following” the CE. One latch at a

time is enabled by the counter’s Control Logic to drive the inter-

nal bus. This is how the 16-bit Counter communicates over the

8-bit internal bus. Note that the CE itself cannot be read; when-

ever you read the count, it is the OL that is being read.

Similarly, there are two 8-bit registers called CRM and CRL (for

“Count Register”). Both are normally referred to as one unit and

called just CR. When a new count is written to the Counter, the

count is stored in the CR and later transferred to the CE. The

Control Logic allows one register at a time to be loaded from

the internal bus. Both bytes are transferred to the CE simulta-

neously. CRM and CRL are cleared when the Counter is pro-

grammed for one byte counts (either most signiﬁcant byte only

or least signiﬁcant byte only) the other byte will be zero. Note

that the CE cannot be written into; whenever a count is written,

it is written into the CR.

The Control Logic is also shown in the diagram. CLK n,

GATE n, and OUT n are all connected to the outside world

through the Control Logic.

82C54 System Interface

The 82C54 is treated by the system software as an array of

peripheral I/O ports; three are counters and the fourth is a

control register for MODE programming.

Basically, the select inputs A0, A1 connect to the A0, A1

address bus signals of the CPU. The

CS can be derived

directly from the address bus using a linear select method or

it can be connected to the output of a decoder.

READ/

WRITE

LOGIC

DATA/

BUS

BUFFER

INTERNAL BUS

OUT 2

GATE 2

CLK 2

OUT 1

GATE 1

CLK 1

OUT 0

GATE 0

CLK 0

- D

FIGURE 2. CONTROL WORD REGISTER AND COUNTER

FUNCTIONS

CONTROL

WORD

COUNTER

INTERNAL BUS

CONTROL

LOGIC

CONTROL

WORD

STATUS

LATCH

STATUS

CLK n

GATE n

OUT n

FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM

82C54

4-5

Operational Description

General

After power-up, the state of the 82C54 is undeﬁned. The

Mode, count value, and output of all Counters are undeﬁned.

How each Counter operates is determined when it is pro-

grammed. Each Counter must be programmed before it can

be used. Unused counters need not be programmed.

Programming the 82C54

Counters are programmed by writing a Control Word and

then an initial count.

All Control Words are written into the Control Word Register,

which is selected when A1, A0 = 11. The Control Word spec-

iﬁes which Counter is being programmed.

By contrast, initial counts are written into the Counters, not

the Control Word Register. The A1, A0 inputs are used to

select the Counter to be written into. The format of the initial

count is determined by the Control Word used.

FIGURE 4. 82C54 SYSTEM INTERFACE

Write Operations

The programming procedure for the 82C54 is very ﬂexible.

Only two conventions need to be remembered:

1.For Each Counter, the Control Word must be written

before the initial count is written.

2. The initial count must follow the count format speciﬁed in the

Control Word (least signiﬁcant byte only, most signiﬁcant byte

only, or least signiﬁcant byte and then most signiﬁcant byte).

Since the Control Word Register and the three Counters have

separate addresses (selected by the A1, A0 inputs), and each

Control Word speciﬁes the Counter it applies to (SC0, SC1 bits),

no special instruction sequence is required. Any programming

sequence that follows the conventions above is acceptable.

Control Word Format

A1, A0 = 11;

CS = 0; RD = 1; WR = 0

D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 RW1 RW0 M2 M1 M0 BCD

ADDRESS BUS (16)

CONTROL BUS

DATA BUS (8)

I/OR I/OW

A1 A0

COUNTER

OUTGATECLK

COUNTER

OUTGATECLK OUTGATECLK

D0 - D7

82C54

SC - Select Counter

SC1 SC0

0 0 Select Counter 0

0 1 Select Counter 1

1 0 Select Counter 2

1 1 Read-Back Command (See Read Operations)

RW - Read/Write

RW1 RW0

0 0 Counter Latch Command (See Read Operations)

0 1 Read/Write least significant byte only.

1 0 Read/Write most significant byte only.

1 1 Read/Write least significant byte first, then most

significant byte.

M - Mode

M2 M1 M0

0 0 0 Mode 0

0 0 1 Mode 1

X 1 0 Mode 2

X 1 1 Mode 3

1 0 0 Mode 4

1 0 1 Mode 5

BCD - Binary Coded Decimal

0 Binary Counter 16-bit

1 Binary Coded Decimal (BCD) Counter (4 Decades)

NOTE: Don’t Care bits (X) should be 0 to insure compatibility with

future products.

Possible Programming Sequence

A1 A0

Control Word - Counter 0 1 1

LSB of Count - Counter 0 0 0

MSB of Count - Counter 0 0 0

Control Word - Counter 1 1 1

LSB of Count - Counter 1 0 1

MSB of Count - Counter 1 0 1

Control Word - Counter 2 1 1

LSB of Count - Counter 2 1 0

MSB of Count - Counter 2 1 0

Possible Programming Sequence

A1 A0

Control Word - Counter 0 1 1

Control Word - Counter 1 1 1

Control Word - Counter 2 1 1

LSB of Count - Counter 2 1 0

82C54

4-6

A new initial count may be written to a Counter at any time

without affecting the Counter’s programmed Mode in any way.

Counting will be affected as described in the Mode deﬁnitions.

The new count must follow the programmed count format.

If a Counter is programmed to read/write two-byte counts,

the following precaution applies. A program must not transfer

control between writing the ﬁrst and second byte to another

routine which also writes into that same Counter. Otherwise,

the Counter will be loaded with an incorrect count.

Read Operations

It is often desirable to read the value of a Counter without

disturbing the count in progress. This is easily done in the

82C54.

There are three possible methods for reading the Counters.

The ﬁrst is through the Read-Back command, which is

explained later. The second is a simple read operation of the

Counter, which is selected with the A1, A0 inputs. The only

requirement is that the CLK input of the selected Counter

must be inhibited by using either the GATE input or external

logic. Otherwise, the count may be in process of changing

when it is read, giving an undeﬁned result.

Counter Latch Command

The other method for reading the Counters involves a spe-

cial software command called the “Counter Latch Com-

mand”. Like a Control Word, this command is written to the

Control Word Register, which is selected when A1, A0 = 11.

Also, like a Control Word, the SC0, SC1 bits select one of

the three Counters, but two other bits, D5 and D4, distin-

guish this command from a Control Word.

The selected Counter’s output latch (OL) latches the count

when the Counter Latch Command is received. This count is

held in the latch until it is read by the CPU (or until the Counter

is reprogrammed). The count is then unlatched automatically

and the OL returns to “following” the counting element (CE).

This allows reading the contents of the Counters “on the ﬂy”

without affecting counting in progress. Multiple Counter Latch

Commands may be used to latch more than one Counter.

Each latched Counter’s OL holds its count until read. Counter

Latch Commands do not affect the programmed Mode of the

Counter in any way.

If a Counter is latched and then, some time later, latched

again before the count is read, the second Counter Latch

Command is ignored. The count read will be the count at the

time the ﬁrst Counter Latch Command was issued.

With either method, the count must be read according to the

programmed format; speciﬁcally, if the Counter is pro-

grammed for two byte counts, two bytes must be read. The

two bytes do not have to be read one right after the other;

read or write or programming operations of other Counters

may be inserted between them.

Another feature of the 82C54 is that reads and writes of the

same Counter may be interleaved; for example, if the

Counter is programmed for two byte counts, the following

sequence is valid.

LSB of Count - Counter 1 0 1

LSB of Count - Counter 0 0 0

MSB of Count - Counter 0 0 0

MSB of Count - Counter 1 0 1

MSB of Count - Counter 2 1 0

Possible Programming Sequence

A1 A0

Control Word - Counter 2 1 1

Control Word - Counter 1 1 1

Control Word - Counter 0 1 1

LSB of Count - Counter 2 1 0

MSB of Count - Counter 2 1 0

LSB of Count - Counter 1 0 1

MSB of Count - Counter 1 0 1

LSB of Count - Counter 0 0 0

MSB of Count - Counter 0 0 0

Possible Programming Sequence

A1 A0

Control Word - Counter 1 1 1

Control Word - Counter 0 1 1

LSB of Count - Counter 1 0 1

Control Word - Counter 2 1 1

LSB of Count - Counter 0 0 0

MSB of Count - Counter 1 0 1

LSB of Count - Counter 2 1 0

MSB of Count - Counter 0 0 0

MSB of Count - Counter 2 1 0

NOTE: In all four examples, all counters are programmed to

Read/Write two-byte counts. These are only four of many

programming sequences.

Possible Programming Sequence (Continued)

A1 A0

A1, A0 = 11; CS = 0; RD = 1; WR = 0

D7 D6 D5 D4 D3 D2 D1 D0

SC1SC000XXXX

SC1, SC0 - specify counter to be latched

SC1 SC0 COUNTER

00 0

01 1

10 2

1 1 Read-Back Command

D5, D4 - 00 designates Counter Latch Command, X - Don’t Care.

NOTE: Don’t Care bits (X) should be 0 to insure compatibility with

future products.

82C54

Part #	IS82C54-10
Description	PERIPH PRG-CNTR 5V 10MHZ 28PLCC IND
Category	IC
Availability	Out of Stock
Qty	0

IS82C54-10

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