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IS41C16257-60K

Part # IS41C16257-60K
Description DRAM Chip FPM 4M-Bit 256Kx165V 40-Pin SOJ
Category IC
Availability In Stock
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ISSI
Date Code: 0051
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
FEATURES
Fast access and cycle time
TTL compatible inputs and outputs
Refresh Interval: 512 cycles/8 ms
Refresh Mode: -Only, -before- (CBR),
and Hidden
JEDEC standard pinout
Single power supply:
-- 5V ± 10% (IS41C16257)
-- 3.3V ± 10% (IS41LV16257)
Byte Write and Byte Read operation via two
Industrial temperature available
DESCRIPTION
The ISSI IS41C16257 and the IS41LV16257 are 262,144
x 16-bit high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 512 random accesses
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
byte, makes these devices ideal for use in 16- and 32-bit
wide data bus systems.
These features make the IS41C16257 and the IS41LV16257
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C16257 and the IS41LV16257 are packaged in a
40-pin, 400-mil SOJ and TSOP (Type II).
IS41C16257
IS41LV16257
256K x 16 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
MAY 1999
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
DR004-1B
05/24/99
KEY TIMING PARAMETERS
Parameter -35 -60 Unit
Max. Access Time (tRAC)3560ns
Max. Access Time (tCAC)1015ns
Max. Column Address Access Time (tAA)1830ns
Min. Fast Page Mode Cycle Time (tPC)1225ns
Min. Read/Write Cycle Time (tRC) 60 110 ns
ISSI
®
IS41C16257
IS41LV16257
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99
ISSI
®
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
262,144 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A8
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A8 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
UCAS Upper Column Address
Strobe
Lower Column Address
Strobe
Vcc Power
GND Ground
NC No Connection
40-Pin SOJ
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
IS41C16257
IS41LV16257
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
DR004-1B
05/24/99
ISSI
®
TRUTH TABLE
Function Address tR/tC I/O
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z
Upper Byte, DIN
Read-Write
(1,2)
LLLHLLH ROW/COL DOUT, DIN
Hidden Refresh
2)
Read LHL L L H L ROW/COL DOUT
Write LHLLLLXROW/COLDOUT
-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh
(3)
HL L L X X X High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either or active).
2. These READ cycles may also be BYTE READ cycles (either or active).
3. At least one of the two CAS signals must be active ( or ).
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