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ICS8543BGI

Part # ICS8543BGI
Description IC CLK BUFFER 2:4 650MHZ 20TSSOP
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ICS8543BG REVISION E DECEMBER 17, 2010 7 ©2010 Integrated Device Technology, Inc.
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter @ 153.6MHz
12kHz to 20MHz = 0.164ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ICS8543BG REVISION E DECEMBER 17, 2010 8 ©2010 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V LVDS Output Load AC Test Circuit
Differential Output Level
Part-to-Part Skew
Differential Input Level
Output Skew
Propagation Delay
SCOPE
Qx
nQx
LVDS
3.3V±5%
POWER SUPPLY
+–
Float GND
V
DD
V
DD
GND
V
OS
Cross Points
V
OD
nQ[0:3]
Q[0:3]
tsk(pp)
Part 1
Part 2
nQx
Qx
nQy
Qy
V
DD
GND
nCLK,
CLK,
V
CMR
Cross Points
V
PP
nPCLK
PCLK
nQx
Qx
nQy
Qy
tsk(o)
CLK,
PCLK
t
PD
nQ[0:3]
Q[0:3]
nCLK,
nPCLK
ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ICS8543BG REVISION E DECEMBER 17, 2010 9 ©2010 Integrated Device Technology, Inc.
Parameter Measurement Information, continued
Output Rise/Fall Time
Offset Voltage Setup
High Impedance Leakage Current Setup
Output Duty Cycle/Pulse Width/Period
Differential Output Voltage Setup
Differential Output Short Circuit Setup
20%
80%
80%
20%
t
R
t
F
V
OD
nQ[0:3]
Q[0:3]
out
out
LVDS
DC Input
V
OS
/ V
OS
V
DD
out
out
LVDS
DC Inpu
t
3.3V±5% POWER SUPPLY
Float GND
+
_
I
OZ
I
OZ
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
nQ[0:3]
Q[0:3]
100
out
out
LVDS
DC Input
V
OD
/ V
OD
V
DD
out
out
LVDS
DC Input
I
OSD
V
DD
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