DATA SHEET

Low Skew, 1-to-4,

Differential-to-LVDS Fanout Buffer

ICS8543

General Description

The ICS8543 is a low skew, high performance 1-to-4

Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage

Differential Signaling (LVDS) the ICS8543 provides a low power, low

noise, solution for distributing clock signals over controlled

impedances of 100Ω. The ICS8543 has two selectable clock inputs.

The CLK, nCLK pair can accept most standard differential input

levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL

input levels. The clock enable is internally synchronized to eliminate

runt pulses on the outputs during asynchronous

assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the

ICS8543 ideal for those applications demanding well defined

performance and repeatability.

Features

• Four differential LVDS output pairs

• Selectable differential CLK, nCLK or LVPECL clock inputs

• CLK, nCLK pair can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• PCLK, nPCLK pair can accept the following differential input

levels: LVPECL, CML, SSTL

• Maximum output frequency: 800MHz

• Translates any single-ended input signals to LVDS levels with

resistor bias on nCLK input

• Additive phase jitter, RMS: 0.164ps (typical)

• Output skew: 40ps (maximum)

• Part-to-part skew: 500ps (maximum)

• Propagation delay: 2.6ns (maximum)

• Full 3.3V supply mode

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

ICS8543

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm

package body

G Package

Top View

Pin Assignment

Block Diagram

nQ0

nQ1

nQ2

nQ3

CLK_EN

CLK

CLK_SEL

Pulldown

nCLK

Pullup

PCLK

Pulldown

nPCLK

Pullup

GND

nPCLK

PCLK

nCLK

CLK

CLK_SEL

CLK_EN

GND

nQ0

nQ1

nQ2

GND

nQ3

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 9, 13 GND Power Power supply ground.

2 CLK_EN Input Pullup

Synchronizing clock enable. When HIGH, clock outputs follows clock input. When

LOW, Qx outputs are forced low, nQx outputs are forced high.

LVCMOS / LVTTL interface levels.

3 CLK_SEL Input Pulldown

Clock select input. When HIGH, selects PCLK, nPCLK inputs.

When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.

4 CLK Input Pulldown Non-inverting differential clock input.

5 nCLK Input Pullup Inverting differential clock input.

6 PCLK Input Pulldown Non-inverting differential LVPECL clock input.

7 nPCLK Input Pullup Inverting differential LVPECL clock input.

8 OE Input Pullup

Output enable. Controls enabling and disabling of outputs Q[0:3], nQ[0:3].

LVCMOS/LVTTL interface levels.

10, 18 V

Power Positive supply pins.

11, 12 nQ3, Q3 Output Differential output pair. LVDS interface levels.

14, 15 nQ2, Q2 Output Differential output pair. LVDS interface levels.

16, 17 nQ1, Q1 Output Differential output pair. LVDS interface levels.

19, 20 nQ0, Q0 Output Differential output pair. LVDS interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Input Capacitance 4pF

PULLUP

Input Pullup Resistor 51 kΩ

PULLDOWN

Input Pulldown Resistor 51 kΩ

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Function Tables

Table 3A. Control Input Function Table

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.

Figure 1. CLK_EN Timing Diagram

Table 3B. Clock Input Function Table

NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.

Inputs Outputs

OE CLK_EN CLK_SEL Selected Source Q[0:3] nQ[0:3]

0 X X Hi-Z Hi-Z

1 0 0 CLK, nCLK Disabled; Low Disabled; High

1 0 1 PCLK, nPCLK Disabled; Low Disabled; High

1 1 0 CLK, nCLK Enabled Enabled

1 1 1 PCLK, nPCLK Enabled Enabled

Inputs Outputs

Input to Output Mode PolarityCLK or PCLK nCLK or nPCLK Q[0:3] nQ[0:3]

0 1 LOW HIGH Differential to Differential Non-Inverting

1 0 HIGH LOW Differential to Differential Non-Inverting

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting

Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting

Enabled

Disabled

CLK_EN

CLK, PCLK

nCLK, nPCLK

Q0:Q3

nQ0:nQ3

Part #	ICS8543BGI
Description	IC CLK BUFFER 2:4 650MHZ 20TSSOP
Category	IC
Availability	Out of Stock
Qty	0

ICS8543BGI

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Technical Document