HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J
High Speed Digital Isolators
Data Sheet
Description
The HCPL-90xx and HCPL-09xx CMOS digital isolators
feature high speed performance and excellent transient
immunity specifications. The symmetric magnetic
coupling barrier gives these devices a typical pulse width
distortion of 2 ns, a typical propagation delay skew of
4 ns and 100 Mbaud data rate, making them the indus-
try’s fastest digital isolators.
The single channel digital isolators (HCPL-9000/
-0900) features an active-low logic output enable.
The dual channel digital isolators are configured as
unidirectional (HCPL-9030/-0930) and bi-directional
(HCPL-9031/-0931), operating in full duplex mode making
it ideal for digital eldbus applications.
The quad channel digital isolators are configured as
unidirectional (HCPL-900J/-090J), two channels in one
direction and two channels in opposite direction (HCPL-
901J/-091J), and one channel in one direction and
three channels in opposite direction (HCPL-902J/-092J).
These high channel density make them ideally suited
to isolating data conversion devices, parallel buses and
peripheral interfaces.
They are available in 8-pin PDIP, 8-pin Gull Wing, 8-pin
SOIC packages, and 16–pin SOIC narrow-body and
wide-body packages. They are specied over the tem-
perature range of -40°C to +100°C.
Features
• +3.3V and +5V TTL/CMOS compatible
• 3 ns max. pulse width distortion
•
6 ns max. propagation delay skew
• 15 ns max. propagation delay
• High speed: 100 MBd
• 15 kV/µs min. common mode rejection
• Tri-state output (HCPL-9000/-0900)
• 2500 V RMS isolation
• UL1577 and IEC 61010-1 approved
Applications
• Digital eldbus isolation
• Multiplexed data transmission
• Computer peripheral interface
• High speed digital systems
• Isolated data interfaces
• Logic level shifting
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
