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GTL2008PW

Part # GTL2008PW
Description Translation - Voltage Levels12-BIT XEON GTL TO LVTTL TRAN
Category IC
Availability In Stock
Qty 42
Qty Price
1 - 8 $1.33320
9 - 17 $1.06050
18 - 26 $0.99990
27 - 35 $0.92920
36 + $0.82820
Manufacturer Available Qty
Philips Semiconductor
Date Code: 0552
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1. General description
The GTL2008/GTL2107 is a customized translator between dual Xeon processors,
Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals.
Functionally and footprint identical to the GTL2007, the GTL2008/GTL2107 LVTTL and
GTL outputs were changed to put them into a high-impedance state when EN1 and EN2
are LOW, with the exception of 11BO because its normal state is LOW, so it is forced
LOW. EN1 and EN2 will remain LOW until V
CC
is at normal voltage, the other inputs are in
valid states and VREF is at its proper voltage to assure that the outputs will remain
high-impedance through power-up.
Both the GTL2008/GTL2107 and the GTL2007 are derived from the GTL2006. They add
an enable function that disables the error output to the monitoring agent for platforms that
monitor the individual error conditions from each processor. This enable function can be
used so that false error conditions are not passed to the monitoring agent when the
system is unexpectedly powered down. This unexpected power-down could be from a
power supply overload, a CPU thermal trip, or some other event of which the monitoring
agent is unaware.
A typical implementation would be to connect each enable line to the system power good
signal or the individual enables to the VRD power good for each processor.
Typically Xeon processors specify a V
TT
of 1.1 V to 1.2 V, as well as a nominal V
ref
of
0.73 V to 0.76 V. To allow for future voltage level changes that may extend V
ref
to 0.63 of
V
TT
(minimum of 0.693 V with V
TT
of 1.1 V) the GTL2008/GTL2107 allows a minimum V
ref
of 0.66 V. Characterization results show that there is little DC or AC performance variation
between these levels.
The GTL2008 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency
comparator that is used in dual-processor Xeon applications.
The GTL2107 is the Intel designation for the GTL2008.
2. Features
n Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
n EN1 and EN2 disable error output
n All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are
LOW
n 3.0 V to 3.6 V operation
n LVTTL I/O not 5 V tolerant
GTL2008; GTL2107
12-bit GTL to LVTTL translator with power good control and
high-impedance LVTTL and GTL outputs
Rev. 02 — 26 September 2006 Product data sheet
GTL2008_GTL2107_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 26 September 2006 2 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
n Series termination on the LVTTL outputs of 30
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds
500 mA
n Package offered: TSSOP28
3. Quick reference data
4. Ordering information
The GTL2107 is the Intel designation for the GTL2008 and is identical to the GTL2008
except for the type number and the topside markings.
Table 1. Quick reference data
T
amb
=25
°
C
Symbol Parameter Conditions Min Typ Max Unit
C
io
input/output capacitance A port; V
O
= 3.0 V or 0 V - 2.5 3.5 pF
B port; V
O
=V
TT
or 0 V - 1.5 2.5 pF
V
ref
= 0.73 V; V
TT
= 1.1 V
t
PLH
LOW-to-HIGH
propagation delay
nA to nBI; see Figure 4 14 8ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
21318ns
t
PHL
HIGH-to-LOW
propagation delay
nA to nBI; see Figure 4 2 5.5 10 ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2 4 10 ns
V
ref
= 0.76 V; V
TT
= 1.2 V
t
PLH
LOW-to-HIGH
propagation delay
nA to nBI; see Figure 4 14 8ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
21318ns
t
PHL
HIGH-to-LOW
propagation delay
nA to nBI; see Figure 4 2 5.5 10 ns
nBI to nA or nAO (open-drain outputs);
see
Figure 14
2 4 10 ns
Table 2. Ordering information
T
amb
=
40
°
C to +85
°
C
Type
number
Topside
mark
Package
Name Description Version
GTL2008PW GTL2008 TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
GTL2107PW GTL2107 TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
GTL2008_GTL2107_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 26 September 2006 3 of 20
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
5. Functional diagram
(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and
the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs.
(2) The 11BO output is driven LOW after V
CC
is powered up with EN2 LOW to prevent reporting of a fault condition before EN2
goes HIGH.
Fig 1. Logic diagram of GTL2008/GTL2107
002aab968
GTL2008/GTL2107
1BI
2BI
27
26
GTL inputs
7BO1
25
7BO2
24
GTL outputs
EN2
23
LVTTL input
11BO
22
GTL output
DELAY
(1)
5BI
6BI
21
20
3BI
19
4BI
18
DELAY
(1)
GTL inputs
7
11BI
8
11A
9
9BI
LVTTL input/output
(open-drain)
GTL input
GTL input
1
VREF
2
1AO
3
2AO
4
5A
5
6A
6
EN1LVTTL input
GTL
LVTTL inputs/outputs
(open-drain)
LVTTL outputs
(open-drain)
10
3AO
11
4AO
LVTTL outputs
(open-drain)
10BO1
17
10BO2
16
GTL outputs
12
10AI1
13
10AI2
LVTTL inputs
9AO
15
LVTTL output
(2)
1
1
&
&
1
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