Specifications GAL6002
3
The GAL6002 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is individually
configurable as asynchronous, latched, or registered inputs. Pin
1 (ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Individually configurable
inputs provide system designers with unparalleled design flexibility.
With the GAL6002, external input registers and latches are not
necessary.
Both the ILMC and the IOLMC are individually configurable and the
ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations and its associated fuse numbers are
shown in the diagrams on the following pages. Note that these
programmable cells are configured by the logic compiler software.
The user does not need to manually manipulate these architecture
bits.
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND array,
are available at the device pins. Cells in this group are known as
Output Logic Macrocells (OLMC).
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinational, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the
programmable polarity control cell called XORD. Polarity selection
for BLMCs is selected through the true and complement forms of
their feedbacks to the AND array. Polarity of all E (Enable) sum
terms is selected through the XORE programmable cells.
When the output or buried logic macrocell is configured as a
D/E type register, the register is clocked from the common OCLK
and the register clock enable input is controlled by the associated
"E" sum term. This configuration is useful for building counters and
state-machines with count hold and state hold functions.
When the macrocell is configured as a D type register with a sum
term clock, the register is always enabled and the associated “E”
sum term is routed directly to the clock input. This permits
asynchronous programmable clocking, selected on a register-by-
register basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. All registers reset
to logic zero. With the inverting output buffers, the output pins will
reset to logic one.
There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer). When the OLMC is used as an output, the second feedback
path is through the IOLMC. With this dual feedback arrangement,
the OLMC can be permanently buried without losing the use of the
associated OLMC pin as an input, or dynamically buried with the
use of the output enable product term.
The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS, JK, and T registers with the same efficiency as a dedicated RS,
JK, or T registers.
The three macrocell configurations are shown in the diagrams on
the following pages. These programmable cells are also configured
by the logic compiler software. The user does not need to manually
manipulate these architecture bits.
Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)
Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)
