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GAL22V10D-15LJ

Part # GAL22V10D-15LJ
Description IC CPLD 10MC 15NS 28PLCC
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Specifications GAL22V10
13
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
su
t
co
t
h
(external fdbk)
1/
f
max
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
CLK
(w/o fdbk)
t
wh
t
wl
1/
f
max
Clock Width
REGISTERED
OUTPUT
CLK
INPUT or
I/O FEEDBACK
DRIVING SP
t
su
t
h
t
co
t
spr
REGISTERED
OUTPUT
CLK
t
arw
t
ar
t
arr
INPUT or
I/O FEEDBACK
DRIVING AR
fmax with Feedback
Asynchronous ResetSynchronous Preset
CLK
REGISTERED
FEEDBACK
t
cf t
su
1/
f
max (internal fdbk)
Switching Waveforms
Specifications GAL22V10
14
fmax with Internal Feedback 1/(tsu+tcf)
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
fmax with External Feedback 1/(tsu+tco)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
REGISTER
LOGIC
ARRAY
CLK
tsu + th
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
fmax Descriptions
Specifications GAL22V10
15
GAL22V10D-4 Output Load Conditions (see figure below)
Test Condition R
1 CL
A50 50pF
B Z to Active High at 1.9V 50 50pF
Z to Active Low at 1.0V 50 50pF
C Active High to Z at 1.9V 50 50pF
Active Low to Z at 1.0V 50 50pF
Input Pulse Levels GND to 3.0V
Input Rise and D-4/-5/-7, C-5 1.5ns 10% 90%
Fall Times D-10/-15/-20/-25 2.0ns 10% 90%
B & C-7/-10
B-15/-20/-25 3ns 10% 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
level.
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
Output Load Conditions (except D-4) (see figure below)
Test Condition R
1 R2 CL
A 300 390 50pF
B Active High 390 50pF
Active Low 300 390 50pF
C Active High 390 5pF
Active Low 300 390 5pF
TEST POINT
Z
0
= 50, C
L
*
FROM OUTPUT (O/Q)
UNDER TEST
+1.45V
R
1
Switching Test Conditions
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