Altera Corporation 29
MAX 3000A Programmable Logic Device Family Data Sheet
Table 17. EPM3032A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
–4 –7 –10
Min Max Min Max Min Max
t
IN
Input pad and buffer delay 0.7 1.2 1.5 ns
t
IO
I/O input pad and buffer
delay
0.7 1.2 1.5 ns
t
SEXP
Shared expander delay 1.9 3.1 4.0 ns
t
PEXP
Parallel expander delay 0.5 0.8 1.0 ns
t
LAD
Logic array delay 1.5 2.5 3.3 ns
t
LAC
Logic control array delay 0.6 1.0 1.2 ns
t
IOE
Internal output enable delay 0.0 0.0 0.0 ns
t
OD1
Output buffer and pad
delay, slow slew rate = off
V
CCIO
= 3.3 V
C1 = 35 pF 0.8 1.3 1.8 ns
t
OD2
Output buffer and pad
delay, slow slew rate = off
V
CCIO
= 2.5 V
C1 = 35 pF 1.3 1.8 2.3 ns
t
OD3
Output buffer and pad
delay, slow slew rate = on
V
CCIO
= 2.5 V or 3.3 V
C1 = 35 pF 5.8 6.3 6.8 ns
t
ZX1
Output buffer enable delay,
slow slew rate = off
V
CCIO
= 3.3 V
C1 = 35 pF 4.0 4.0 5.0 ns
t
ZX2
Output buffer enable delay,
slow slew rate = off
V
CCIO
= 2.5 V
C1 = 35 pF 4.5 4.5 5.5 ns
t
ZX3
Output buffer enable delay,
slow slew rate = on
V
CCIO
= 2.5 V or 3.3 V
C1 = 35 pF 9.0 9.0 10.0 ns
t
XZ
Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns
t
SU
Register setup time 1.3 2.0 2.8 ns
t
H
Register hold time 0.6 1.0 1.3 ns
t
RD
Register delay 0.7 1.2 1.5 ns
t
COMB
Combinatorial delay 0.6 1.0 1.3 ns
t
IC
Array clock delay 1.2 2.0 2.5 ns
t
EN
Register enable time 0.6 1.0 1.2 ns
t
GLOB
Global control delay 0.8 1.3 1.9 ns
t
PRE
Register preset time 1.2 1.9 2.6 ns
t
CLR
Register clear time 1.2 1.9 2.6 ns
